參數(shù)資料
型號(hào)： CY37064VP44-YMB
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： EE PLD, 12 ns, CQCC44
封裝： CERAMIC, LCC-44
文件頁(yè)數(shù)： 11/66頁(yè)
文件大小： 1259K
代理商： CY37064VP44-YMB
Ultra37000 CPLD Family
19
Switching Characteristics Over the Operating Range[11]
Parameter
Description
Unit
Combinatorial Mode Parameters
tPD
[12, 13, 14]
Input to Combinatorial Output
ns
tPDL
[12, 13, 14]
Input to Output Through Transparent Input or Output Latch
ns
tPDLL
[12, 13, 14]
Input to Output Through Transparent Input and Output Latches
ns
tEA
[12, 13, 14]
Input to Output Enable
ns
tER
[10, 12]
Input to Output Disable
ns
Input Register Parameters
tWL
Clock or Latch Enable Input LOW Time[8]
ns
tWH
Clock or Latch Enable Input HIGH Time[8]
ns
tIS
Input Register or Latch Set-Up Time
ns
tIH
Input Register or Latch Hold Time
ns
tICO
[12, 13, 14]
Input Register Clock or Latch Enable to Combinatorial Output
ns
tICOL
[12, 13, 14]
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
ns
Synchronous Clocking Parameters
tCO
[13, 14]
Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output
ns
tS
[12]
Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable
ns
tH
Register or Latch Data Hold Time
ns
tCO2
[12, 13, 14]
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
ns
tSCS
[12]
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous
Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)
ns
tSL
[12]
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0
CLK1, CLK2, or CLK3) or Latch Enable
ns
tHL
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0,
CLK1, CLK2, or CLK3) or Latch Enable
ns
Product Term Clocking Parameters
tCOPT
[12, 13, 14]
Product Term Clock or Latch Enable (PTCLK) to Output
ns
tSPT
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
ns
tHPT
Register or Latch Data Hold Time
ns
tISPT
[12]
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
ns
tIHPT
Buried Register Used as an Input Register or Latch Data Hold Time
ns
tCO2PT
[12, 13, 14]
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
ns
Pipelined Mode Parameters
tICS
[12]
Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous
Clock (CLK0, CLK1, CLK2, or CLK3)
ns
Notes:
11. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
12. Logic Blocks operating in Low-Power Mode, add tLP to this spec.
13. Outputs using Slow Output Slew Rate, add tSLEW to this spec.
14. When VCCO= 3.3V, add t3.3IO to this spec.
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