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| 型號： | CY3120R62 |
| 英文描述： | Programmable Logic |
| 中文描述： | 可編程邏輯 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 67K |
| 代理商： | CY3120R62 |
CY3120
Document #: 38-03049 Rev. *C
Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Page 7 of 8
Timing Analyzer
The Timing Analyzer graphically reports the time across any
path as well as the breakdown of what steps are causing the
timing delays. This tool does not simply display the general
specification for the target device but a worst-case simulation
of the actual path being taken through the device. When you
highlight a path on the timing analyzer, the source an desti-
nation of that path are displayed on the Architecture Explorer.
The timing analyzer is available for PSI and Delta39K devices.
Programming
Cypress’s F
LASH
370i, Ultra37000, and Delta39K In-System
Reprogrammable (ISR) devices can be programmed on
board with an ISR programmer. For Delta39K CPLDs
Warp
produces an Intel hex file. The ISR programmer converts this
file into STAPL and programs the device. For Ultra37000 and
F
LASH
370i devices,
Warp
produces a JEDEC file. For
Ultra37000, the ISR programmer converts this file into
JAM/STAPL and programs the device. For F
LASH
370i, the
JEDEC file is used directly to program the device.
The JEDEC and Intel hex files produced by
Warp
can also be
used with any qualified third party programmer to program
Cypress CPLDs.
For more information on Cypress’s ISR software see the ISR
Programming Kit (CY3900i) data sheet.
System Requirements
IBM PC or equivalent (Pentium
class recommended)
32 MB of RAM (64 MB recommended)
110 MB Disk Space
CD-ROM drive
Windows 98, Windows NT 4.0, Windows XP
Internet access to download upgrades
Warp
includes:
CD-ROM with
Warp
, Aldec Active-HDL Sim and FSM, and
on-line documentation (
Getting Started Manual, User’s
Guide, HDL Reference Manual
)
VHDL for Programmable Logic
textbook
Registration card
Intel and Pentium are registered trademarks of Intel Corporation. Windows 95, Windows 98, Windows 2000, Windows NT and
Windows XP are trademarks of Microsoft Corporation. Solaris is a trademark of Sun Microsystems Corporation. Active-HDL is a
trademark of Aldec Incorporated.
Warp
is a registered trademark, and
Warp
Enterprise, UltraGen, PSI, Ultra37000, Delta39K,
PSI, Programmable Serial Interface, MAX340, ISR, In-System Reprogrammable, and F
LASH
370i are trademarks, of Cypress
Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
Product Ordering Information
Product Code
CY3120R62
Description
Warp
development system for PCs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY3121-ADAPTER | 功能描述:插座和適配器 Eval Kit Adapter RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| CY3121-CUSTOMER | 功能描述:開發(fā)軟件 WARP2 VHDL COMPILER PLD/CPLD ONLY-PC VER RoHS:否 制造商:Atollic Inc. 產(chǎn)品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CY3125 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Warp CPLD Development Tool for UNIX |
| CY3125R62 | 功能描述:TOOL DEVELOPMENT CPLD FOR UNIX RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 軟件 系列:- 標準包裝:1 系列:ISE® 設(shè)計套件 類型:訂閱 適用于相關(guān)產(chǎn)品:Xilinx FPGAs 其它名稱:Q4986209T1081384 |
| CY3128 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Warp Professional CPLD Software |
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