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參數(shù)資料
| 型號： | CY3120R62 |
| 英文描述： | Programmable Logic |
| 中文描述： | 可編程邏輯 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 67K |
| 代理商： | CY3120R62 |
CY3120
Document #: 38-03049 Rev. *C
Page 4 of 8
ENTITY seg7 IS
PORT(
inputs: IN STD_LOGIC_VECTOR (0 to 3)
outputs: OUT STD_LOGIC_VECTOR (0 to 6)
);
END SEG7;
ARCHITECTURE mixed OF seg7 IS
CONSTANT truthTable:
ttf_table (0 to 11, 0 to 10) := (
-- input&
output
-- -----------------------
”0000”&
”0111111”,
”0001”&
”0000110”,
”0010”&
”1011011”,
”0011”&
”1001111”,
”0100”&
”1100110”,
”0101”&
”1101101”,
”0110”&
”1111101”,
”0111”&
”0000111”,
”1000”&
”1111111”,
”1001”&
”1101111”,
”101-”&
”1111100”, --creates E pattern
”111-”&
”1111100”
);
BEGIN
outputs <= ttf(truthTable,inputs);
END mixed;
Boolean Equations
A third design-entry method available to
Warp
users is Boolean
equations.
Figure 2
displays a schematic of a simple one-bit
half adder. The following code describes how this one-bit half
adder can be implemented in Warp with Boolean equations:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--entity declaration
ENTITY half_adder IS
PORT (x, y : IN std_logic;
sum, carry : OUT std_logic);
END half_adder;
--architecture body
ARCHITECTURE behave OF half_adder IS
BEGIN
sum <= x XOR y;
carry <= x AND y;
END behave;
Structural VHDL
While all of the design methodologies described thus far are
high-level entry methods, structural VHDL provides a method
for designing at a very low level. In structural descriptions, the
designer simply lists the components that make up the design
and specifies how the components are wired together.
Figure 3
displays the schematic of a simple three-bit shift
register and the following code shows how this design can be
described in Warp using structural VHDL:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.rtlpkg.all;
ENTITY shifter3 IS port (
clk : IN STD_LOGIC;
x : IN STD_LOGIC;
q0 : OUT STD_LOGIC;
q1 : OUT STD_LOGIC;
q2 : OUT STD_LOGIC);
END shifter3;
ARCHITECTURE struct OF shifter3 IS
SIGNAL q0_temp, q1_temp, q2_temp : STD_LOGIC;
BEGIN
d1 : DFF PORT MAP(x,clk,q0_temp);
d2 : DFF PORT MAP(q0_temp,clk,q1_temp);
d3 : DFF PORT MAP(q1_temp,clk,q2_temp);
q0 <= q0_temp;
q1 <= q1_temp;
q2 <= q2_temp;
END struct;
All of the design-entry methods described can be mixed as
desired. VHDL has the ability to combine both high- and
low-level entry methods in a single file. The flexibility and
power of VHDL allows users of
Warp
to describe designs using
whatever method is appropriate for their particular design.
A Verilog Design Example
Design Entry
Warp
descriptions specify:
The behavior or structure of a design.
The mapping of signals in a design to the pins of a
PLD/CPLD (optional).
The part of a Warp description that specifies the behavior or
structure of the design is called a module. The module
declares the design’s interface signals (i.e., defines what
external signals the design has, and what their directions and
types are).
Figure 2. One-Bit Half Adder
x
y
carry
sum
1
Figure 3. Three-Bit Shift Register Circuit Design
clk
d
q
clk
d
q
clk
d
q
x
clk
q0
q1
q2
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