參數(shù)資料
型號： CY2SSTV857ZC-32
廠商： SILICON LABORATORIES
元件分類： 時鐘及定時
英文描述： PLL BASED CLOCK DRIVER, PDSO48
封裝： 0.240 INCH, MO-153, TSSOP-48
文件頁數(shù)： 2/8頁
文件大小： 90K
代理商： CY2SSTV857ZC-32
CY2SSTV857
.......................... Document #: 38-07557 Rev. *E Page 2 of 8
Pin Description
Pin #
48 TSSOP
Pin #
40 QFN
Pin Name
I/O[1]
Pin Description
Electrical
Characteristics
13, 14
5,6
CLK, CLK#
I
Differential Clock Input.
LV Differential Input
35
25
FBIN#
I
Feedback Clock Input. Connect to FBOUT# for
accessing the PLL.
Differential Input
36
26
FBIN
I
Feedback Clock Input. Connect to FBOUT for
accessing the PLL.
3, 5, 10, 20, 22
37,39,3,12,14
Y(0:4)
O
Clock Outputs.
Differential Outputs
2, 6, 9, 19, 23
36,40,2,11,15
Y#(0:4)
O
Clock Outputs.
27, 29, 39, 44, 46 17,19,29,32,34
Y(9:5)
O
Clock Outputs.
Differential Outputs
26, 30, 40, 43, 47 16,20,30,31,35
Y#(9:5)
O
Clock Outputs.
32
21
FBOUT
O
Feedback Clock Output. Connect to FBIN for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
Differential Outputs
33
22
FBOUT#
O
Feedback Clock Output. Connect to FBIN# for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
37
27
PD#
I
Power Down Input. When PD# is set HIGH, all
Q and Q# outputs are enabled and switch at the
same frequency as CLK. When set LOW, all Q
and Q# outputs are disabled Hi-Z and the PLL
is powered down.
4, 11,12,15, 21,
28, 34, 38, 45
4,7,13,18,23,24,
28,33,38
VDDQ
2.6V Power Supply for Output Clock Buffers.2.6V Nominal
16
8
AVDD
2.6V Power Supply for PLL. When VDDA is at
GND, PLL is bypassed and CLK is buffered
directly to the device outputs. During disable
(PD# = 0), the PLL is powered down.
2.6V Nominal
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
1,10
VSS
Common Ground.
0.0V Ground
17
9
AVSS
Analog Ground.0.0V Analog
Ground
Note:
1. A bypass capacitor (0.1
F) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
40 QFN
CY2SSTV857-32
19
18
17
16
15
14
13
12
11
20
Y3
#
y3
VD
D
Q
Y4
#
Y9
#
Y9
VD
D
Q
Y8
Y8#
32
33
34
35
36
37
38
39
40
31
Y1#
Y1
VD
D
Q
Y0
Y0#
Y5#
Y5
VD
D
Q
Y6
#
30
29
28
27
26
25
24
23
22
21
Y7#
VDDQ
Y7
PD#
FBIN
FBIN#
VDDQ
FBOUT#
FBOUT
1
2
3
4
5
6
7
8
9
10
VSS
Y2
Y2#
VDDQ
CLK
CLK#
VDDQ
AVDD
AVSS
VSS
40 QFN Package
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CY2SSTV857ZI-32T 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver DDR400/PC3200-Compliant
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