參數(shù)資料
型號: CY2SSTV857LFC-32
元件分類: 時鐘及定時
英文描述: SSTV SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
封裝: 6 X 6 MM, QFN-40
文件頁數(shù): 4/8頁
文件大?。?/td> 103K
代理商: CY2SSTV857LFC-32
CY2SSTV857-32
Rev 1.0, November 21, 2006
Page 4 of 8
CLKIN
t
pd
Yx or FBIN
Figure 2. Propagation Delay Time tPLH, tPHL
t
C(n+1)
Yx
t
C(n)
Figure 3. Cycle-to-cycle Jitter
PLL
FBIN
FBIN#
120
Ohm
120
Ohm
CLK
CLK#
DDR -
SDRAM
120
Ohm
VTR
VCP
0.3"
= 2.5"
= 0.6" (Split to Terminator)
DDR _SDRAM
represents a capacitive load
DDR -
SDRAM
FBOUT#
FBOUT
Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< 8 pF
Figure 4. Clock Structure # 1
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參數(shù)描述
CY2SSTV857LFC-32[15] 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Differential Clock Buffer/Driver DDR400/PC3200-Compliant
CY2SSTV857LFC-32T 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Differential Clock Buffer/Driver DDR400/PC3200-Compliant
CY2SSTV857LFC-32T[15] 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Differential Clock Buffer/Driver DDR400/PC3200-Compliant
CY2SSTV857LFI-32 制造商:Cypress Semiconductor 功能描述:
CY2SSTV857LFI-32[15] 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Differential Clock Buffer/Driver DDR400/PC3200-Compliant