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參數(shù)資料
| 型號： | CY29775 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 74K |
| 代理商： | CY29775 |
CY29774
Document #: 38-07479 Rev. **
Page 5 of 9
Note:
6.
AC characteristics apply for parallel output termination of 50
to V
TT
. Parameters are guaranteed by characterization and are not 100% tested.
I
DDA
I
DDQ
I
DD
C
IN
Z
OUT
PLL Supply Current
A
VDD
only
All V
DD
pins except A
VDD
Outputs loaded @ 100 MHz
–
5
10
mA
Quiescent Supply Current
–
–
1
mA
Dynamic Supply Current
–
225
–
mA
Input Pin Capacitance
–
4
–
pF
Output Impedance
12
15
18
AC Electrical Specifications
[6]
(V
DD
= 2.5V ± 5%, T
A
= –40°C to +85°C)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
f
VCO
f
in
VCO Frequency
200
–
400
MHz
Input Frequency
÷
8 Feedback
÷
12 Feedback
÷
16 Feedback
÷
24 Feedback
÷
32 Feedback
÷
48 Feedback
25
–
50
MHz
16.6
–
33.3
12.5
–
25
8.3
–
16.6
6.3
–
12.5
4.2
–
8.3
Bypass mode (PLL_EN = 0)
0
–
200
f
refDC
t
r
, t
f
f
MAX
Input Duty Cycle
25
–
75
%
TCLK Input Rise/FallTime
0.7V to 1.7V
–
–
1.0
ns
Maximum Output Frequency
÷
4 Output
÷
8 Output
÷
12 Output
÷
16 Output
÷
24 Output
50
–
100
MHz
25
–
50
16.6
–
33.3
12.5
–
25
8.3
–
16.6
DC
Output Duty Cycle
45
–
55
%
t
r
, t
f
t
(
φ
)
Output Rise/Fall times
0.7V to 1.8V
0.1
–
1.0
ns
Propagation Delay (static phase
offset)
TCLK to FB_IN, does not
include jitter
–100
–
100
ps
t
sk(O)
tsk(B)
Output-to-Output Skew
Skew within Bank
–
–
150
ps
Bank-to-Bank Skew
Banks at same frequency
–
–
150
ps
Banks at different frequency
–
–
225
t
PLZ, HZ
t
PZL, ZH
BW
Output Disable Time
–
–
10
ns
Output Enable Time
–
–
10
ns
PLL Closed Loop Bandwidth (–3 dB)
–
0.5 - 1.0
–
MHz
t
JIT(CC)
Cycle-to-Cycle Jitter
Same frequency
–
–
150
ps
Multiple frequencies
–
–
300
t
JIT(PER)
t
JIT(
φ
)
t
LOCK
Period Jitter
–
–
100
ps
I/O Phase Jitter
–
–
150
ps
Maximum PLL Lock Time
–
–
1
ms
DC Electrical Specifications
(V
DD
= 3.3V ± 5%, T
A
= –40°C to +85°C) (continued)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29775AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY29775AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| CY29775AXI | 功能描述:鎖相環(huán) - PLL 2.5/3.3V 200MHz LVCMOS I/O 14 ZDB RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29775AXIT | 功能描述:鎖相環(huán) - PLL 2.5/3.3V 200MHz LVCMOS I/O 14 ZDB RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2977AAXI | 制造商:Cypress Semiconductor 功能描述: |
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