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參數(shù)資料
| 型號(hào)： | CY29775 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 74K |
| 代理商： | CY29775 |
CY29774
Document #: 38-07479 Rev. **
Page 2 of 9
Notes:
1.
2.
PU = Internal pull up, PD = Internal pull down
A 0.1-
μ
F bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply
pins.
3.
Pin Description
[1]
Pin
Name
I/O
Type
Description
9
TCLK0
I, PD
LVCMOS
LVCMOS/LVTTL reference clock input
10
TCLK1
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input
16, 18, 21,
23, 25
QA(4:0)
O
LVCMOS
Clock output bank A
32, 34, 36,
38, 40
QB(4:0)
O
LVCMOS
Clock output bank B
44, 46, 48,
50
QC(3:0)
O
LVCMOS
Clock output bank C
29
FB_OUT
O
LVCMOS
Feedback clock output
. Connect to FB_IN for normal operation.
31
FB_IN
I, PU
LVCMOS
Feedback clock input
. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference clock.
See
Table 1
.
2
MR#/OE
I, PU
LVCMOS
Output enable/disable input
. See
Table 2
.
3
CLK_STP#
I, PU
LVCMOS
Clock stop enable/disable input
. See
Table 2
.
6
PLL_EN
I, PU
LVCMOS
PLL enable/disable input
. See
Table 2
.
8
TCLK_SEL
I, PD
LVCMOS
Reference select input
. See
Table 2
.
52
VCO_SEL
I, PD
LVCMOS
VCO divider select input
. See
Table 2
.
7, 4, 5
SEL(A:C)
I, PD
LVCMOS
Frequency select input, Bank (A:C)
. See
Table 3
.
20, 14
FB_SEL(1,0)
I, PD
LVCMOS
Feedback dividers select input
. See
Table 4
.
2.5V or 3.3V Power supply for bank A output clocks
[2,3]
2.5V or 3.3V Power supply for bank B output clocks
[2,3]
2.5V or 3.3V Power supply for bank C output clocks
[2,3]
2.5V or 3.3V Power supply for feedback output clock
[2,3]
2.5V or 3.3V Power supply for PLL
[2,3]
2.5V or 3.3V Power supply for core and inputs
[2,3]
17, 22, 26
VDDQA
Supply
VDD
33, 37, 41
VDDQB
Supply
VDD
45, 49
VDDQC
Supply
VDD
28
VDDFB
Supply
VDD
13
AVDD
Supply
VDD
12
VDD
Supply
VDD
15
AVSS
Supply
Ground
Analog Ground
1, 19, 24,
30, 35, 39,
43, 47, 51
VSS
Supply
Ground
Common Ground
11, 27, 42
NC
No Connection
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PDF描述 |
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| CY29940-1 | Clocks and Buffers |
| CY29976 | Clocks and Buffers |
| CY29977 | Clocks and Buffers |
| CY29FCT520ATDM | Pipeline Register |
| CY29FCT520ATLM | Pipeline Register |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29775AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY29775AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer |
| CY29775AXI | 功能描述:鎖相環(huán) - PLL 2.5/3.3V 200MHz LVCMOS I/O 14 ZDB RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29775AXIT | 功能描述:鎖相環(huán) - PLL 2.5/3.3V 200MHz LVCMOS I/O 14 ZDB RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2977AAXI | 制造商:Cypress Semiconductor 功能描述: |
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