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參數(shù)資料
| 型號(hào)： | CY29774 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 74K |
| 代理商： | CY29774 |
CY29774
Document #: 38-07479 Rev. **
Page 6 of 9
AC Electrical Specifications
[6]
(V
DD
= 3.3V ± 5%, T
A
= –40°C to +85°C)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
f
VCO
f
in
VCO Frequency
200
–
500
MHz
Input Frequency
÷
8 Feedback
÷
12 Feedback
÷
16 Feedback
÷
24 Feedback
÷
32 Feedback
÷
48 Feedback
25
–
62.5
MHz
16.6
–
41.6
12.5
–
31.25
8.3
–
20.8
6.25
–
15.625
4.2
–
10.4
Bypass mode (PLL_EN = 0)
0
–
200
f
refDC
t
r
, t
f
f
MAX
Input Duty Cycle
25
–
75
%
TCLK Input Rise/FallTime
0.8V to 2.0V
–
1.0
ns
Maximum Output Frequency
÷
4 Output
÷
8 Output
÷
12 Output
÷
16 Output
÷
24 Output
50
–
125
MHz
25
–
62.5
16.6
–
41.6
12.5
–
31.25
8.3
–
20.8
DC
Output Duty Cycle
45
–
55
%
t
r
, t
f
t
(
φ
)
Output Rise/Fall times
0.8V to 2.4V
0.1
–
1.0
ns
Propagation Delay (static phase
offset)
TCLK to FB_IN, same V
DD
,
does not include jitter
–100
–
100
ps
t
sk(O)
t
sk(B)
Output-to-Output Skew
Skew within Bank
–
–
150
ps
Bank-to-Bank Skew
Banks at same voltage,
same frequency
–
–
150
ps
Banks at same voltage,
different frequency
–
–
225
Banks at different voltage
–
–
250
t
PLZ, HZ
t
PZL, ZH
BW
Output Disable Time
–
–
10
ns
Output Enable Time
–
–
10
ns
PLL Closed Loop Bandwidth
(–3dB)
–
0.5 - 1.0
–
MHz
t
JIT(CC)
Cycle-to-Cycle Jitter
Same frequency
–
–
150
ps
Multiple frequencies
–
–
300
t
JIT(PER)
t
JIT(
φ
)
t
LOCK
Period Jitter
–
–
100
ps
I/O Phase Jitter
I/O at same V
DD
–
–
150
ps
Maximum PLL Lock Time
–
–
1
ms
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| CY29775 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
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