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參數(shù)資料
| 型號(hào)： | CY29774 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 74K |
| 代理商： | CY29774 |
CY29774
Document #: 38-07479 Rev. **
Page 3 of 9
Table 1. Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
25 MHz to 62.5 MHz
Input Frequency Range
(AVDD = 2.5V)
25 MHz to 50 MHz
÷
8
÷
12
÷
16
÷
24
÷
32
÷
48
Input Clock * 8
Input Clock * 12
16.6 MHz to 41.6 MHz
16.6 MHz to 33.3 MHz
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 25 MHz
Input Clock * 24
8.3 MHz to 20.8 MHz
8.3 MHz to 16.6 MHz
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 12.5 MHz
Input Clock * 48
4.2 MHz to 10.4 MHz
4.2 MHz to 8.3 MHz
Table 2. Function Table (configuration controls)
Control
TCLK_SEL
VCO_SEL
PLL_EN
Default
0
0
1
0
1
TCLK0
TCLK1
VCO
÷
2 (high input frequency range)
Bypass mode, PLL disabled. The input clock
connects to the output dividers
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL feedback
loop is open and the VCO running at its minimum
frequency. The device is reset by the internal
power-on reset (POR) circuitry during power-up.
QA, QB, and QC outputs disabled in LOW state.
FB_OUT is not affected by CLK_STP#.
VCO
÷
4 (low input frequency range)
PLL enabled. The VCO output
connects to the output dividers
Outputs enabled
MR#/OE
1
CLK_STP#
1
Outputs enabled
Table 3. Function Table (Bank A, B and C)
VCO_SEL
0
0
1
1
SELA
0
1
0
1
QA(4:0)
÷
4
÷
8
÷
8
÷
16
SELB
0
1
0
1
QB(4:0)
÷
4
÷
8
÷
8
÷
16
SELC
0
1
0
1
QC(3:0)
÷
8
÷
12
÷
16
÷
24
Table 4. Function Table (FB_OUT)
VCO_SEL
0
0
0
0
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
FB_OUT
÷
8
÷
16
÷
12
÷
24
÷
16
÷
32
÷
24
÷
48
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|---|---|
| CY29774AI | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 52-Pin TQFP |
| CY29774AIT | 制造商:Cypress Semiconductor 功能描述: |
| CY29774AXI | 功能描述:鎖相環(huán) - PLL ZERO DELAY PLL 125 MHz 14 OUTPUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29774AXIT | 功能描述:鎖相環(huán) - PLL ZERO DELAY PLL 125 MHz 14 OUTPUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29775 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
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