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參數(shù)資料
| 型號(hào)： | CY28419ZXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 11/15頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK SERV CK419 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類(lèi)型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:25 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
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CY28419
........................Document #: 38-07444 Rev. *D Page 5 of 15
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
0
Reserved
6
1
Reserved
5
0
Reserved
4
0
Reserved
3
1
Reserved
2
1
Reserved
1
Externally
Selected
FS_B
FS_B reflects the value of the FS_B pin sampled on power-up.
0 = FS_B low at power-up
0
Externally
Selected
FS_A
FS_A reflects the value of the FS_A pin sampled on power-up.
0 = FS_A low at power-up
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
0
SRCT, SRCC
Allow control of SRCT/C with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
6
1
SRCT, SRCC
SRCT/C Output Enable
0 = Disabled (three-state), 1 = Enabled
5
1
Reserved
4
1
Reserved
3
1
Reserved
2
1
CPUT2, CPUC2
CPUT/C2 Output Enable
0 = Disabled (three-state), 1 = Enabled
1
CPUT1, CPUC1
CPUT/C1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
0
1
CPUT0, CPUC0
CPUT/C0 Output Enable
0 = Disabled (three-state), 1 = Enabled
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
0
SRCT, SRCC
SRCT/C Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
6
0
SRCT, SRCC
SRCT/C Stop drive mode
0 = Driven in PCI_STP, 1 = Three-state in power-down
5
0
CPUT2, CPUC2
CPUT/C2 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
4
0
CPUT1, CPUC1
CPUT/C1 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
3
0
CPUT0, CPUC0
CPUT/C0 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
2
0
Reserved
1
0
Reserved
0
Reserved
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