參數(shù)資料
型號： CY28373
英文描述： Clocks and Buffers
中文描述： 時鐘和緩沖器
文件頁數(shù)： 6/17頁
文件大?。?/td> 240K
代理商： CY28373
CY28312B-2
Document #: 38-07596 Rev. **
Page 6 of 17
Bit 2
Bit 1
Bit 0
13
11
10
PCI2
PCI1
PCI0
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 3: Control Register
Bit
Pin#
9
22
–
21
46
–
47
48
Name
Default
1
1
0
1
1
0
1
1
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCI_F
PCI9_E
Reserved
PCI8
REF2
Reserved
REF1
REF0
(Active/Inactive)
(Active/Inactive)
Reserved
(Active/Inactive)
(Active/Inactive)
Reserved
(Active/Inactive)
(Active/Inactive)
Byte 4: Watchdog Timer Register
Bit
Pin#
–
–
Name
Default
0
0
Description
Bit 7
Bit 6
Reserved
FS_Override
Reserved
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
These bits store the time-out value of the Watchdog
timer. The scale of the timer is determine by the
prescaler.
The timer can support a value of 150 ms to 4.8 sec
when the prescaler is set to 150 ms. If the prescaler is
set to 2.5 sec, it can support a value from 2.5 sec to 80
sec.
When the Watchdog timer reaches “0”, it will set the
WD_TO_STATUS bit.
0 = 150 ms
1 = 2.5 sec
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
–
–
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
1
1
1
1
1
Bit 0
–
WD_PRE_SCAL
ER
0
Byte 5: Control Register 5
Bit
Pin#
9
7
6
47
48
–
–
–
Name
Default
X
X
X
X
X
0
0
0
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Latched FS4 input
Latched FS3 input
Latched FS2 input
Latched FS1 input
Latched FS0 input
Reserved
Reserved
SEL4
Latched FS[4:0] inputs. These bits are read-only.
Reserved
Reserved
SW Frequency selection bits. See
Table 4
.
Byte 6: Reserved Register
Bit
Name
Default
1
1
1
1
Description
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 2: Control Register 2
(continued)
Bit
Pin#
Name
Default
Description
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