參數(shù)資料
型號： CY28370
英文描述： Clocks and Buffers
中文描述： 時鐘和緩沖器
文件頁數(shù)： 14/17頁
文件大小： 240K
代理商： CY28370
CY28312B-2
Document #: 38-07596 Rev. **
Page 14 of 17
AC Electrical Characteristics
T
A
= 0°C to +70°C, V
DDQ3
= 3.3V±5%, f
XTL
= 14.31818 MHz
AC clock parameters are tested and guaranteed over stated
operating conditions using the stated lump capacitive load at
the clock output; Spread Spectrum is disabled.
C
OUT
L
IN
Output Pin Capacitance
Input Pin Inductance
6
7
pF
nH
DC Electrical Characteristics
T
A
= 0°C to +70°C, V
DD
= 3.3V ± 5% and 2.5V ± 5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)
[6]
Parameter
t
R
t
F
t
D
t
JC
f
ST
Description
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle to Cycle
Frequency Stabilization
from Power-up (cold
start)
Test Condition/Comments
CPU_CS
CPU_CS
Measured at 50% point
CPU = 100 MHz
Min.
Typ.
1.0
1.0
45
CPU = 133 MHz
Min.
Typ.
1.0
1.0
45
Unit
V/ns
V/ns
%
ps
ms
Max.
4.0
4.0
55
250
Max.
4.0
4.0
55
250
Assumes full supply voltage reached
within 1 ms from power-up. Short
cycles exist prior to frequency
stabilization.
V
O
= V
X
3
3
Z
o
AC Output Impedance
50
50
W
PCI Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
t
JC
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.8V to 2.0V
Measured from 2.0V to 0.8V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum difference
of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/PCI outputs. Measured on rising edge
at 1.5V. CPU leads PCI output.
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
Average value during switching transition. Used for
determining series termination value.
Min.
30
12
12
1
1
45
Typ.
Max.
Unit
ns
ns
ns
V/ns
V/ns
%
ps
Period
High Time
Low Time
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
4
4
55
250
t
SK
t
O
Output Skew
CPU to PCI Clock Skew
500
4
ps
ns
1.5
f
ST
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
3
ms
Z
o
30
AGP Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
t
R
t
F
t
D
t
JC
Description
Test Condition/Comments
Measured from 0.8V to 2.0V
Measured from 2.0V to 0.8V
Measured at 1.5V
Measured on rising edge at 1.5V. Maximum difference
of cycle time between two adjacent cycles.
Min.
0.5
0.5
45
Typ.
Max.
2.0
2.0
55
250
Unit
V/ns
V/ns
%
ps
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Note:
6. Refer to
Figure 1
for K7 operation clock driver test circuit.
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