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參數(shù)資料
| 型號(hào)： | CY28316 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 2/17頁(yè) |
| 文件大小： | 240K |
| 代理商： | CY28316 |
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CY28312B-2
Document #: 38-07596 Rev. **
Page 2 of 17
Pin Definitions
Pin Name
REF0/FS0
Pin No.
48
Pin
Type
I/O
Pin Description
Reference Clock Output 0/Frequency Select 0
. 3.3V 14.318-MHz clock
output. REF0 will be disabled when REF_STOP# is active. This pin also serves
as the select strap to determines device operating frequency as described in
Table 4
.
Reference Clock Output 0/Frequency Select 1
. 3.3V 14.318-MHz clock
output. REF1 will be disabled when REF_STOP# is active. This pin also serves
as the select strap to determines device operating frequency as described in
Table 4
.
Reference Clock Output 2
. 3.3V 14.318-MHz clock output. REF2 will be
disabled when REF_STOP# is active.
Crystal Input
. This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
Crystal Output
. An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left unconnected.
Free-Running PCI Clock/Frequency Select 4
. 3.3V 33-MHz free running PCI
clock output. This pin also serves as the select strap to determines device
operating frequency as described in
Table 4
.
PCI Clock 0/Select 24 or 48 MHz
. 3.3V 33-MHz PCI clock outputs. This output
will be disabled when PCI_STOP# is active. This pin also serves as the select
strap to determine device operating frequency of 24_48MHz output.
PCI Clock 1 through 8
. 3.3V 33-MHz PCI clock outputs. PCI1:8 will be disabled
when PCI_STOP# is active.
Early PCI Clock 9
. 3.3V 33-MHz PCI clock outputs. PCI9_E will be disabled
when PCI_STOP# is active.
AGP Clock 0 through 2
.
3.3V 66-MHz clock outputs. The operating frequency
is controlled by FS0:4 (see
Table 4
). AGP0:2 will be disabled when
AGP_STOP# is active.
48-MHz Output/Frequency Selection 3
. 3.3V 48-MHz non-spread spectrum
output. 48 MHz will be disabled when REF_STOP# is active. This pin also
serves as the select strap to determine device operating frequency as described
in
Table 4
.
24- or 48-MHz Output/Select 24 or 48 MHz
. 3.3V 24 or 48-MHz non-spread
spectrum output. 24_48MHz will be disabled when REF_STOP# is active. This
pin also serves as the select strap to determine device operating frequency as
described in
Table 4
.
Reset#
.
Open-drain RESET# output.
REF1/FS1
47
I/O
REF2
46
I/O
X1
3
I
X2
4
I
PCI_F/FS4
9
I
PCI_0/SEL24_48#
10
I/O
PCI1:8
11, 13, 14, 16,
17, 18, 20, 21
22
O
PCI9_E
O
AGP0:2
26, 27, 28
O
48MHz/FS2
6
I/O
24_48MHz/FS3
7
I/O
RST#
24
O
(open-
drain)
O
(open-
drain)
O
CPUT0, CPUC0
42, 41
CPU Clock Output 0
.
CPUT0 and CPUC0 are the
differential CPU clock
outputs for the K7 processor. They are open-drain outputs.
CPUT_CS,
CPUC_CS
39, 38
CPU Clock Output for Chipset
.
CPUT_CS and CPUC_CS are the
differential
CPU clock outputs for the chipset. They are push-pull outputs. These outputs
will be disabled when CPU_STOP# is active.
CPU STOP Input
. This input will disable CPUT_CS and CPUC_CS when it is
active.
PCI STOP Input
. This input will disable PCI0:8 and PCI9_E when it is active.
AGP STOP Input
. This input will disable AGP0:2 when it is active.
REF STOP Input
. This input will disable REF0:2, 24_48MHz and 48 MHz
outputs when it is active.
Power-down Input
. This input will trigger the clock generator into Power-down
mode when it is active.
CPU_STOP#
36
I
PCI_STOP#
AGP_STOP#
REF_STOP#
35
44
45
I
I
I
PD#
34
I
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相關(guān)代理商/技術(shù)參數(shù) |
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| CY28317-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Mobile VIA⑩ PL133T and PLE133T Chipsets |
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