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參數(shù)資料
| 型號(hào)： | CY28316 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 240K |
| 代理商： | CY28316 |
CY28312B-2
Document #: 38-07596 Rev. **
Page 10 of 17
Byte 17: Reserved Register
Bit
Pin#
–
–
–
–
–
–
–
Name
Default
0
0
0
0
0
0
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
FS2
SEL3
SEL2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Output Frequency
PLL Gear
Constants
(G)
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
Reserved
Reserved
Reserved
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
FS4
SEL4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3
FS1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
156.0
154.0
152.0
147.0
144.0
142.0
138.0
136.0
124.0
122.0
117.0
115.0
113.0
108.0
105.0
102.0
Reserved
Reserved
Reserved
200.0
190.0
180.0
170.0
150.0
140.0
120.0
110.0
66.6
200.0
166.6
100.0
133.3
3V66
78.0
77.0
76.0
73.5
72.0
71.0
69.0
68.0
62.0
61.0
78.0
76.7
75.3
72.0
70.0
68.0
Reserved
Reserved
Reserved
66.6
76.0
72.0
68.0
75.0
70.0
60.0
73.3
66.6
66.6
66.6
66.6
66.6
PCI
39.0
38.5
38.0
36.8
36.0
35.5
34.5
34.0
31.0
30.5
39.0
38.3
37.7
36.0
35.0
34.0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Reserved
Reserved
Reserved
33.3
38.0
36.0
34.0
37.5
35.0
30.0
33.3
33.3
33.3
33.3
33.3
33.3
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY28316_02 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA PL133T and PLE133T |
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