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| 型號： | CY28312B-2 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 240K |
| 代理商： | CY28312B-2 |
CY28312B-2
Document #: 38-07596 Rev. **
Page 12 of 17
How to Program CPU Output Frequency
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
Fcpu = G * (N + 3)/(M + 3).
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in
Table 4
. The ratio of (N + 3) and (M + 3) needs to be
greater than “1” [(N + 3)/(M + 3) > 1].
Table 6
lists set of N and M values for different frequency
output ranges.This example use a fixed value for the M-Value
Register and select the CPU output frequency by changing the
value of the N-Value Register.
WD_TIMER[4:0]
These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the
prescaler.
The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the pre-scaler
is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.
When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.
0 = 150 ms
1 = 2.5 sec
This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs.
0 = Disabled
1 = Enabled
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled
WD_PRE_SCALER
RST_EN_WD
RST_EN_FC
Table 5. Register Summary
(continued)
Name
Description
Table 6. Examples of N and M Value for Different CPU Frequency Range
Frequency Ranges
50 MHz–129 MHz
130 MHz–248 MHz
Gear Constants
48.00741
48.00741
Fixed Value for
M-Value Register
93
48
Range of N-Value Register
for Different CPU Frequency
97–255
127–245
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