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參數(shù)資料
| 型號： | CY2412SC |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|SOP|8PIN|PLASTIC |
| 中文描述： | 雜項時鐘發(fā)生器|?？苵 8引腳|塑料 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 92K |
| 代理商： | CY2412SC |
CY2410
Document #: 38-07317 Rev. *D
Page 4 of 7
Absolute Maximum Conditions
Parameter
Description
Min.
–0.5
–65
–
Max.
7.0
125
125
V
DD
+ 0.3
V
DD
+ 0.3
Unit
V
°C
°C
V
V
V
V
DD
T
S
T
J
Supply Voltage
Storage Temperature
[3]
Junction Temperature
Digital Inputs
Digital Outputs referred to V
DD
Electrostatic Discharge
V
SS
– 0.3
V
SS
– 0.3
2000
Recommended Operating Conditions
Parameter
Description
Min.
3.135
0
–
–
0.05
Typ.
3.3
–
–
13.5
–
Max.
3.465
70
15
–
500
Unit
V
°C
pF
MHz
ms
V
DD
T
A
C
LOAD
f
REF
t
PU
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Reference Frequency
Power up time for V
DD
to reach minimum speci-
fied voltage
(power ramp must be monotonic)
DC Electrical Specifications
Parameter
I
OH
I
OL
I
OH
I
OL
C
IN
I
IZ
f
XO
Name
Description
Min.
12
12
6
6
–
–
+150
+115
0
–
Typ.
24
24
18
18
–
5
–
–
–
30
Max.
–
–
–
–
7
–
–
–
V
DD
35
Unit
mA
mA
mA
mA
pF
μ
A
ppm
ppm
V
mA
Output HIGH Current –1,3,5,7
Output LOW Current –1,3,5,7
Output HIGH Current –4,6
Output LOW Current –4,6
Input Capacitance
Input Leakage Current
V
CXO
pullability range:–1,–3,–4,–5,–6
V
CXO
pullability range:–7
V
CXO
input range
Supply Current
V
OH
= V
DD
– 0.5, V
DD
= 3.3V
V
OL
= 0.5, V
DD
= 3.3V
V
OH
= V
DD
– 0.5, V
DD
= 3.3V
V
OL
= 0.5, V
DD
= 3.3V
V
VCXO
I
VDD
AC Electrical Specifications (V
DD
= 3.3V)
[4]
Parameter
[4]
DC
Output Duty Cycle
ER
OR
Rising Edge Rate –1, –3, –5, –7 Output Clock Edge Rate, Measured from 20%
Name
Description
Min.
45
0.8
Typ.
50
1.4
Max.
55
–
Unit
%
V/ns
Duty Cycle is defined in
Figure 4
, 50% of V
DD
to 80% of V
DD
, CLOAD = 15 pF See
Figure 5
.
ER
OF
Falling Edge Rate –1, –3, –5, –7 Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, CLOAD = 15 pF See
Figure 5
.
Rising Edge Rate –4, –6
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, CLOAD = 15 pF See
Figure 5
.
Falling Edge Rate –4, –6
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, CLOAD = 15 pF See
Figure 5
.
Clock Jitter –1, –3, –5, –7
Peak-to-peak period jitter
Clock Jitter –4, –6
Peak-to-peak period jitter
PLL Lock Time
0.8
1.4
–
V/ns
ER
OR
0.7
1.1
–
V/ns
ER
OF
0.7
1.1
–
V/ns
t
9
t
9
t
10
Notes:
3. Rated for ten years.
4. Not 100% tested.
–
–
–
140
150
–
–
–
3
ps
ps
ms
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