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參數(shù)資料
| 型號(hào)： | CY2412SC |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|SOP|8PIN|PLASTIC |
| 中文描述： | 雜項(xiàng)時(shí)鐘發(fā)生器|?？苵 8引腳|塑料 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | CY2412SC |
CY2410
Document #: 38-07317 Rev. *D
Page 3 of 7
Se
rial Programmable Interface Protocol
The CY2410-3 utilizes a two-wire-interface SDAT and SCLK
that operates up to 400 kbits/sec in Read or Write mode. The
basic Write serial format is as follows: start bit; 7-bit device
address (DA); R/W bit; slave clock acknowledge (ACK); 8-bit
memory address (MA); ACK; 8-bit data; ACK; 8-bit data in
MA+1 if desired; ACK; 8-bit data in MA+2; ACK; etc. until stop
bit, as illustrated in
Figure 1
.
1-bit
Data Valid
Data is valid when the clock is HIGH, and may only be transi-
tioned when the clock is low as illustrated in
Figure 2
.
Data Frame
Every new data frame is indicated by a start and stop
sequence, as illustrated in
Figure 3
.
Start Sequence
A start frame is indicated by SDAT going LOW when SCLK is
HIGH. Every time a start signal is given, the next 8-bit data
must be the device address (7 bits) and a R/W bit (0 for Write),
followed by register address (8 bits) and register data (8 bits).
See
Figure 3
.
Stop Sequence
A stop frame is indicated by SDAT going HIGH when SCLK is
HIGH. A stop frame frees the bus for writing to another part on
the same bus or writing to another random register
address. See
Figure 3
.
Acknowledge Pulse
During Write mode, the CY2410-3 will respond with an ACK
pulse after every 8 bits. This is accomplished by pulling the
SDAT line LOW during the next clock cycle after the eighth bit
is shifted in.
Device Address
The 7-bit device address is 1101001.
Register Address
The 8-bit address for the VCXO register is 00010011.
Register Data
The register data can be any value between 00H–FFH. As you
increase the value, the capacitance on the X
IN
and X
OUT
pins
will increase, thereby decreasing the xtal frequency.
SDA Write
Start Signal
D7-bit
Address
R/W = 0
1-bit
8-bit
Register
Address
Slave
ACK
ACK
Slave
8-bit
Register
Data
Stop Signal
ACK
Slave
Figure 1. Data Frame Architecture
SDAT
SCLK
Data Valid
Transition
to next bit
CLK
LOW
CLK
HIGH
V
IH
V
IL
t
SU
t
DH
Figure 2. Data Valid and Data Transition Periods
START
Transition
to next bit
STOP
SDAT
SCLK
Figure 3. Start and Stop Frame
Figure 4. Duty Cycle Definition; DC = t2/t1
t1
t2
50%
50%
CLK
Figure 5. Rise and Fall Time Definitions: ER = 0.6 x
VDD / t3, EF = 0.6 x VDD / t4
CLK
t3
t4
80%
20%
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相關(guān)代理商/技術(shù)參數(shù) |
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| CY2412SC-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
| CY2412SC-1T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
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| CY2412SC-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
| CY2412SC-3T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
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