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參數(shù)資料
| 型號： | CY23S09 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 169K |
| 代理商： | CY23S09 |
CY23S05
CY23S09
Document #: 38-07296 Rev. *B
Page 5 of 9
Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H Industrial Temperature Devices
[8]
Parameter
Description
Test Conditions
30-pF load
10-pF load
Min.
10
10
40.0
45.0
Typ.
Max.
100
133.33
60.0
55.0
1.50
1.50
250
Unit
MHz
MHz
%
%
ns
ns
ps
t1
Output Frequency
Duty Cycle
[7]
= t
2
÷
t
1
Duty Cycle
[7]
= t
2
÷
t
1
Rise Time
[7]
Fall Time
[7]
Output-to-Output Skew
[7]
Delay, REF Rising Edge to
CLKOUT Rising Edge
[7]
Measured at 1.4V, F
out
= 66.67 MHz
Measured at 1.4V, F
out
<50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
50.0
50.0
t3
t
4
t
5
t
6
Measured at V
DD
/2
0
±350
ps
t
7
Device-to-Device Skew
[7]
Measured at V
DD
/2 on the CLKOUT
pins of devices
Measured between 0.8V and 2.0V using
Test Circuit #2
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock
presented on REF pin
0
700
ps
t
8
Output Slew Rate
[7]
1
V/ns
t
J
Cycle-to-Cycle Jitter
[7]
200
ps
t
LOCK
PLL Lock Time
[7]
1.0
ms
Switching Waveforms
Duty Cycle Timing
t
1
2309
–
4
t
2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
2309
–
5
OUTPUT
t
3
3.3V
0V
0.8V
2.0V
2.0V
0.8V
t
4
Output-Output Skew
2309
–
6
1.4V
1.4V
t
5
OUTPUT
OUTPUT
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY23S09_04 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low-Cost 3.3V Spread Aware⑩ Zero Delay Buffer |
| CY23S09_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low Cost 3.3V Spread Aware Zero Delay Buffer |
| CY23S09OC-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low Cost 3.3V Spread Aware Zero Delay Buffer |
| CY23S09OC-1H | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low Cost 3.3V Spread Aware Zero Delay Buffer |
| CY23S09OXC-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Low Cost 3.3V Spread Aware Zero Delay Buffer |
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