參數(shù)資料
型號(hào)： CY2308ZI-5
英文描述： Eight Distributed-Output Clock Driver
中文描述： 八分布式輸出時(shí)鐘驅(qū)動(dòng)器
文件頁(yè)數(shù)： 4/9頁(yè)
文件大小： 110K
代理商： CY2308ZI-5
CY23020-3
Document #: 38-07473 Rev. *A
Page 4 of 9
Table 6. V
DDC
= 3.3V ±5%, V
DD
= 3.3V ±5%
(See Test Set-ups, C
L
= 5 pF)
Parameter
Description
I
DD
Min.
Max.
100
Unit
μ
A
I
PD
I
IL
I
IH
Power-down Current
70°C, V
DD
max
V
IN
= 0
V
IN
= V
DD
10
μ
A
100
μ
A
Table 5. PECL DC Output Specification
(continued)
[4]
Parameter
Description
Conditions
V
CC
= 3.135
Min.
V
CC
= 3.3
Min.
V
CC
= 3.465
Min.
Max.
Max.
Max.
Condition
Min.
Typ.
Max.
300
Unit
mA
Loaded, V
DD
max, Cold, 400 MHz,
all outputs switching
C
IN
C
L[5]
V
ISW
V
IX[6]
REF or FBIN ± Pin Capacitance
Load Cap
Single Ended Input Swing
Input Crossover Voltage
(expressed relative to V
DD
)
Input Slew Rate
4
5
5
6
pF
pF
V
0.5
1.25
V
DD
– 1.79
V
DD
– 0.96
S
I
Measured from V
IX MEAS
+ 0.15 to
V
IX MEAS
–0.15. (20– 80% of a min
input swing sig.)
0.9
4
V/ns
V
OSW
V
OX[7]
Single Ended Output Swing
Output Crossing Point
0.6
1.1
V
VO
MID
= (VH_
MEAS
VL_
MEAS
)/2
VO
MID
= (VH_
MEAS
VL_
MEAS
)/2
VO
MID
–
0.20
V
DD
– 1.79
VO
MID
– 0.20
V
OX[8]
Output Crossing Point (relative
to V
DD
)
V
DD
– 0.96
Table 7. V
DDC
= 3.3V ±5%, V
DD
= 3.3V ±5%
(See Test Set-ups, C
L
= 5 pF)
Parameter
Description
S
O
Output Rise/Fall Slew
Rate
D
I
Input Duty Cycle
D
O
Output Duty Cycle
T
PDIO
REFin-FBin prop delay
T
PDIOD
REFin-FBin prop delay
T
PDO
FBout to any output prop
delay
T
PDOB
T
PDOB133
T
TB
Total Timing Budget
T
JCCPP
Cycle-Cycle Jitter (1000
cycles) p-p
T
JCCRMS
RMS Cycle-Cycle Jitter
Tjccop
Tjrms
Condition
Min.
0.9
Typ.
Max.
2
Unit
V/ns
Measured from V
IX MEAS
+ 0.15 to V
IX MEAS
–0.15.
(20–80% of a min input swing sig.)
Input duty cycle
Differential crossing point
External feedback REF, FB same frequency
External feedback REF, FB same frequency x2
40
45
–50
–50
–325
60
55
200
150
–100
%
%
ps
ps
ps
Output-Output skew within a bank
Output-Output skew @133 MHz
150
ps
ps
ps
ps
75
400
100
REF and outputs, same frequency
REF and outputs, same frequency
Ref = x2
Ref = x2
15
125
30
ps
ps
ps
Notes:
5.
6.
Same as input. PECL is assumed to drive single point loads.
This is the output DC mid-voltage range ± the crossover voltage tolerance. Refer Input Voltage is assumed to be derived from same supply as part. This is why
it is spec’d relative to V
.
Crossover is within ± 20% of the center of the minimum swing.
Crossover is within ± 20% of the center of the minimum swing.
7.
8.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY2308ZI-5H 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V Zero Delay Buffer
CY2308ZXC-1H 功能描述:時(shí)鐘緩沖器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
CY2308ZXC-1HKN 制造商:Cypress Semiconductor 功能描述:
CY2308ZXC-1HT 功能描述:時(shí)鐘緩沖器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
CY2308ZXC-5H 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V Zero Delay Buffer
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