- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366974 > CY2308ZI-5 Eight Distributed-Output Clock Driver PDF資料下載
參數(shù)資料
| 型號(hào)： | CY2308ZI-5 |
| 英文描述： | Eight Distributed-Output Clock Driver |
| 中文描述： | 八分布式輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大小： | 110K |
| 代理商： | CY2308ZI-5 |
CY23020-3
Document #: 38-07473 Rev. *A
Page 3 of 9
How to Implement Zero Delay
Typically, ZDBs multiply (fan-out) single-clock signals quantity
while simultaneously reducing or mitigating the time delay
associated with passing the clock through a buffering device.
In many cases the output clock is adjusted, in phase, to occur
later or more often before the device’s input clock to
compensate for a design’s physical delay inadequacies. Most
commonly this is done using a simple PCB trace as a time
delay element. The longer the trace the earlier the output clock
edges occur with respect to the reference input clock edges.
In this way such effects as undesired transit time of a clock
signal across a PCB can be compensated for.
Inserting Other Devices in Feedback Path
Due to the fact that the device has an external feedback path
the user has a wide range of control over its output to input
skewing effect. One of these is to be able to synchronize the
outputs of an external clock that is resultant from any of the
output clocks. This implementation can be applied to any
device (ASIC, multiple output clock buffer/driver, etc.) which is
put into the feedback path.
Referring to
Figure 1
, if the traces between the ASIC/buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin (B), the
signals at the destination(s) device (C) will be driven high at
the same time the Reference clock provided to the ZDB goes
high. Synchronizing the other outputs of the ZDB to the outputs
from the ASIC/Buffer is more complex however, as any propa-
gation delay in the ASIC/Buffer must be accounted for.
There are constraints when inserting other devices. If the
devices contain PLLs or excessively long delay times they can
easily cause the overall clocking system to become unstable
as the components interact. For these designs it is advisable
to contact Cypress for applications support.
Table 2. Frequency Range Setting
RANGE
0
1
Output Frequency Range
100–200 MHz
200–400 MHz
Table 3. Frequency Multiplication Table
MUL
0
1
Output Frequency
= REF
= 2 * REF
Reference
Signal
Feedback
Input
ASIC/
Buffer
Zero
Delay
Buffer
A
B
C
Figure 1. Output Buffer in Feedback Path
Table 4. Absolute Maximum Ratings
[3]
Parameter
V
DD
V
IN
T
STG
T
A
T
J
Table 5. PECL DC Output Specification
[4]
Description
Rating
Unit
V
V
°C
°C
°C
Voltage on any V
DD
pin with respect to GND
Voltage on any input pin with respect to GND
Storage Temperature
Operation Temperature (QFN)
Junction Temperature
–0.5 to +5.0
–0.5 to V
DD
+ 0.5
–65 to +150
–40 to 85
135
Parameter
Description
Conditions
V
CC
= 3.135
Min.
V
CC
= 3.3
Min.
2
V
CC
= 3.465
Min.
2.165
Max.
Max.
2.6
Max.
2.765
V
OH
V
OL
V
OH
(rel to V
CC
)
1.835
2.435
1.135
–1.3
1.735
–0.7
1.3
1.9
–0.7
1.465
–1.3
2.065
–0.7
–1.3
V
OL
(rel to V
CC
)
–2
–1.4
–2
–1.4
–2
–1.4
These result in the following mid point values:
[4]
V
MID
((V
OH +
V
OL
)/2)
V
MID
Relative to V
CC
Notes:
3.
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at
these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may
affect reliability.
4.
The midpoint voltage is average value of a waveform. For differential signals the midpoint is assumed to be the same for both the true and complement since
the V
and V
of both the true and complement signals in general should be the same. V
MID
is not necessarily equal to the differential crossover voltage,
which may be skewed if there is differential time delays between the signals.
1.485
2.085
1.65
2.25
1.815
2.415
–1.65
–1.05
–1.65
–1.05
–1.65
–1.05
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2303 | Clocks and Buffers |
| CY2303SC | THREE DISTRIBUTED-OUTPUT CLOCK DRIVER|SOP|8PIN|PLASTIC |
| CY2303SI | THREE DISTRIBUTED-OUTPUT CLOCK DRIVER|SOP|8PIN|PLASTIC |
| CY2308SC-1HT | Eight Distributed-Output Clock Driver |
| CY2308SC-1T | Eight Distributed-Output Clock Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2308ZI-5H | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V Zero Delay Buffer |
| CY2308ZXC-1H | 功能描述:時(shí)鐘緩沖器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2308ZXC-1HKN | 制造商:Cypress Semiconductor 功能描述: |
| CY2308ZXC-1HT | 功能描述:時(shí)鐘緩沖器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2308ZXC-5H | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V Zero Delay Buffer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。