參數(shù)資料
型號(hào): CY2308SI-1H
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: 3.3V Zero Delay Buffer
中文描述: 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, MS-012, SOIC-16
文件頁數(shù): 11/17頁
文件大?。?/td> 502K
代理商: CY2308SI-1H
CY2308
Document Number: 38-07146 Rev. *K
Page 3 of 17
Pinouts
Figure 1. Pin Diagram - 16 Pin SOIC (Top view)
Table 1. Pin Definitions - 16 Pin SOIC
Pin
Signal
Description
1
REF[1]
Input reference frequency
2
CLKA1[2]
Clock output, Bank A
3
CLKA2[2]
Clock output, Bank A
4VDD
Power supply voltage
5
GND
Power supply ground
6
CLKB1[2]
Clock output, Bank B
7
CLKB2[2]
Clock output, Bank B
8
S2[3]
Select input, bit 2
9
S1[3]
Select input, bit 1
10
CLKB3[2]
Clock output, Bank B
11
CLKB4[2]
Clock output, Bank B
12
GND
Power supply ground
13
VDD
Power supply voltage
14
CLKA3[2]
Clock output, Bank A
15
CLKA4[2]
Clock output, Bank A
16
FBK
PLL feedback input
Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
Output Source
PLL Shutdown
0
Tri-state
PLL
Y
0
1
Driven
Tri-state
PLL
N
10
Driven[4]
Reference
Y
1
Driven
PLL
N
9
16
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
4. Outputs inverted and PLL bypass mode for 2308–2 and 2308–3, S2 = 1 and S1 = 0.
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