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參數(shù)資料
| 型號： | CXD2411R |
| 英文描述： | Signal Generator for LCD |
| 中文描述： | 信號發(fā)生器的液晶顯示器 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大?。?/td> | 1286K |
| 代理商： | CXD2411R |
CXD2403AR
–23–
HSYNC Separation
HSYNC is separated from the composite sync input.
Noise is eliminated with the counter and equivalent
pulse is eliminated with the half H killer.
H-DET
Noise Elimination
Half H-Kill
SKEW DET
H Counter
(Matching the number of H)
(Internal pulse)
AFH
SYNC
PLL
H Control
Circuit
Noise
Shape
V-Reset pulse
(internal pulse)
SYNC
V-RESET
Pulse
Generate
V-SYNC Separation Circuit
V-SYNC Period
190μs
SYNC
NOISE SHAPE START
AA
NOISE
SHAPED
PULSE
V-RESET
PULSE
NOISE SHAPE END
AA
When the pulse enters in this
period, twice the pulse time
width is added.
V-SYNC
Decision Period
125μs
V-SYNC Input Time Axis Specification
A
B
C
D
E
F
HSYNC jumping detection and address management
when jumping occurs frequently (matching the number
of H in a field) are also performed.
V. SYNC Separation
V. sync is separated from the composite sync input
connected to SYNC connector. The serration pulses
are removed as noise. When considerable pulse width
is detected, the V reset pulse is output to notify V sync
input and to synchronize timing of output signals. When
a V sync having different pulse width from normal one is
input, it can be separated when the width of serration
pulse is narrower than 2~3 μsec or less which is
positioned right after the V sync having 0.5H width
during A~F period.
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| CXD24-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CXD2412AQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Timing Generator for LCD Panels |
| CXD24-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CXD2422R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CCD Camera Timing Generator |
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