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參數(shù)資料
| 型號： | CXD2411R |
| 英文描述： | Signal Generator for LCD |
| 中文描述： | 信號發(fā)生器的液晶顯示器 |
| 文件頁數(shù)： | 22/25頁 |
| 文件大?。?/td> | 1286K |
| 代理商： | CXD2411R |
–22–
CXD2403AR
Driving for No Signal
HST, HCK1, HCK2, FRP, VCK1, VCK2, XCLP, HD,
VD, and VST are made to run free so that the liquid
crystal panel is AC driven even when there is no
composite sync from the SYNC pin.
The PLL counter is made to run free because the
HSYNC separation circuit stops. In addition, the
auxiliary V counter is used to create the reference pulse
for generating VD and VST because the VSYNC
separation circuit is also stopped.
4.7μs
2.5V
0V
5V
Center of SYNC
SYNC
RPD
The period of the V counter is 269H for NTSC and
321H for PAL, and if there is no VSYNC during
269H/321H, it is assumed to be a no signal state.
The RPD pin is kept at high impedance so that the
AFC circuit does not cause phase errors by phase
comparison.
AFC Circuit
(638/702 fh clock generation)
A fully synchronized AFC circuit is built in. PLL error
detection signal is generated at the following timing.
The phase comparison output of the entire bottom of
SYNC and the internal H counter becomes RPD. RPD
output is converted to DC error with the lag-lead filter.
Then the outputs change the vari-cap capacitance and
the oscillating frequency is stabilized at 638 fh in
LCX003/1004 or 702 fh in LCX005.
Example of PLL Related Peripheral Circuit
RPD
CKI
CKO
1k
10k
33k
1000pF
3300pF
3.3μ
L
100pF
0.01μ
10k
100k
1T369
+12V
37
40
39
+
L value
LCX003/004
LCX005
→
8.2μ
→
6.8μ
*The parameters of the elements are reference.
Parts : Vari-cap
1T369 (Sony), MA365 (Matsushita)
Adjustment Method
1. Adjust the voltage for vari-cap with the variable
resistor connected to 12V power supply while checking
HSYNC and RPD waveforms with an oscilloscope.
Concretely, adjust so that the RPD rise is at the center
of HSYNC.
2. When PLL is still not locked, change the L of the LC
oscillations.
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