參數(shù)資料
型號(hào): CXA7004R
英文描述: LCD Driver
中文描述: LCD驅(qū)動(dòng)器
文件頁(yè)數(shù): 15/25頁(yè)
文件大小: 274K
代理商: CXA7004R
– 15 –
CXA7004R
Horizontal sync timing <PRPOL>
The horizontal sync signal PRG is also used as the internal circuit reset function.
The Mode setting: PRPOL sets whether to apply the reset at the rising edge or the falling edge of PRG.
The reset is applied at the rising edge of the PRG pulse when PRPOL is high, and at the falling edge of the
PRG pulse when PRPOL is low.
Output phase setting <FHCNT>
The SIG_OUT output timing phase can be set by the Mode setting: FHCNT.
When FHCNT is low, all SIG_OUT outputs are output at the same timing. When FHCNT is high, SIG_OUT1 to
SIG_OUT3 and SIG_OUT4 to SIG_OUT6 are output at phases offset by 1/2 clock period from each other.
Polarity setting <FRINV>
Output polarity inversion/non-inversion relative to the signal center voltage is set by the FRP input and the
external pin FRINV (Pin 29). When set to the combinations shown in the table below, SIG_OUT is output non-
inverted (solid line) or inverted (dotted line) relative to FRP.
FRINV: H
Non-inverted
Inverted
FRP: H
FRP: L
FRINV: L
Inverted
Non-inverted
FRP
SIG_C
SIG_OUT
GND
Inverted
Non-inverted
PRG
MCLK
Reset pulse
PRPOL: H
PRPOL: L
SIG_OUT4 to 6
SIG_OUT1 to 3
GND
SIG_OUT4 to 6
SIG_OUT1 to 3
GND
FHCNT: L
FHCNT: H
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