參數(shù)資料
型號(hào)： CXA7004R
英文描述： LCD Driver
中文描述： LCD驅(qū)動(dòng)器
文件頁(yè)數(shù)： 14/25頁(yè)
文件大?。?/td> 274K
代理商： CXA7004R
– 14 –
CXA7004R
Other settings are as follows.
Mode setting
The CXA7004R can be set to master/slave mode, single mode, and right/left inversion, etc. This makes it
possible to support various systems. (Various mode setting is designated with register and external pins.)
The various operating modes are described below.
Operating mode setting <SLDAT>
The digital input of two ICs can be used together in master/slave mode by setting the Mode setting: SLDAT to
high level, or single mode can be set by setting SLDAT to low level. In master/slave mode, the 12-bit input is
shorted between the two ICs, and the ODD or EVEN data is selected by STATUS (Pin 30), DIRC (Pin 31) and the
Mode setting: DIRCR. Input a clock having the same period as the input data rate to CLK (Pin 34) in both modes.
SLDAT: L
SIG_OUT1: 1
SIG_OUT2: 2
SIG_OUT3: 3
SIG_OUT4: 4
SIG_OUT5: 5
SIG_OUT6: 6
SIG_OUT1: 6
SIG_OUT2: 5
SIG_OUT3: 4
SIG_OUT4: 3
SIG_OUT5: 2
SIG_OUT6: 1
SLDAT: H
SIG_OUT1: 2
SIG_OUT2: 4
SIG_OUT3: 6
SIG_OUT4: 8
SIG_OUT5: 10
SIG_OUT6: 12
SIG_OUT1: 11
SIG_OUT2: 9
SIG_OUT3: 7
SIG_OUT4: 5
SIG_OUT5: 3
SIG_OUT6: 1
SIG_OUT1: 1
SIG_OUT2: 3
SIG_OUT3: 5
SIG_OUT4: 7
SIG_OUT5: 9
SIG_OUT6: 11
SIG_OUT1: 12
SIG_OUT2: 10
SIG_OUT3: 8
SIG_OUT4: 6
SIG_OUT5: 4
SIG_OUT6: 2
DIRC ex-or DIRCR: H
DIRC ex-or DIRCR: L
STATUS: L
STATUS: H
Clock polarity setting <CKPOL>
The polarity of the internal circuit operation clock (MCLK) is determined by the Mode setting: CKPOL.
The internal circuits operate at reverse polarity from CLK when CKPOL is high, and at the same polarity as CLK
when CKPOL is low.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Input data D_IN[11:0]
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