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參數(shù)資料
| 型號： | CXA3627N |
| 英文描述： | All Band Tuner IC with On-chip PLL |
| 中文描述： | 所有波段調(diào)諧器集成電路片上鎖相環(huán) |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 230K |
| 代理商： | CXA3627N |
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CXA3627N
3) Control format
When performing control for this IC, byte 1 contains the address data, bytes 2 and 3 contain the frequency
data, byte 4 contains the control data, and byte 5 contains the band switch data.
These data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5.
When the correct address is received and acknowledged, the data is recognized as frequency data if the
first bit of the next byte is "0", and as control data and band switch data if this bit is "1".
Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore, once
the control and band switch data have been programmed, 3-byte commands consisting of the address and
frequency data are possible.
Further, even if the I
2
C bus stop conditions are not met, data can be input by sending the start conditions
and the new address.
The control format is as shown in the table below.
Slave Receiver
X: Don't care
A:
MA0, MA1:
M0 to:
S0 to:
CD:
OS:
CP:
GC:
BS1 to BS4: band switch control (output PNP transistor ON when "1")
R0, R1:
reference divider frequency division ratio setting (See the Reference Divider Frequency Division
Ratio Table.)
Acknowledge bit
address setting
main divider frequency division ratio setting
swallow counter frequency division ratio setting
charge pump OFF (when "1")
varicap output OFF (when "1")
charge pump current switching (200μA when "1", 50μA when "0")
gain switching (IC gain reduced by 2dB when "1")
Reference Divider Frequency Division Ratio Table
MSB
bit 7
1
0
M2
1
X
bit 6
1
M9
M1
CP
X
bit 5
0
M8
M0
GC
X
bit 4
0
M7
S4
CD
X
bit 3
0
M6
S3
X
BS4
bit 2
MA1
M5
S2
R1
BS3
bit 1
MA0
M4
S1
R0
BS2
LSB
bit 0
0
M3
S0
OS
BS1
A
A
A
A
A
Address byte
Divider byte1
Divider byte2
Control byte
Band SW byte
Mode
X: Don't care
R1
0
1
X
R0
1
1
0
Reference Divider
256
128
160
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