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參數(shù)資料
| 型號： | CXA3627N |
| 英文描述： | All Band Tuner IC with On-chip PLL |
| 中文描述： | 所有波段調(diào)諧器集成電路片上鎖相環(huán) |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 230K |
| 代理商： | CXA3627N |
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16
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CXA3627N
Description of PLL Block
This IC is controlled by the I
2
C bus.
The PLL of this IC performs high-speed phase comparison, providing low reference leak and quick lock-up
time characteristics.
During power on, the power-on reset circuit operates to initialize the frequency data to all "0" and the band
data to all "OFF". Power-on reset is performed when V
CC
≥
3.2V at room temperature (Ta = 25
°
C).
1) Address setting
Up to four addresses can be selected by the hardware bit settings, so that multiple PLL can exist within one
system.
The responding address can be set according to the ADSW pin voltage.
Address
1
1
0
0
0
MA1
MA0
R/W
MA1
0
0
1
1
MA0
0
1
0
1
ADSW pin voltage
0 to 0.1Vcc
OPEN or
0.2Vcc to 0.3Vcc
0.4Vcc to 0.6Vcc
0.9Vcc to Vcc
Hardware bits
2) Frequency data setting
The VCO lock frequency is obtained according to the following formula.
fosc = 2
×
fref
×
(32M + S)
fosc: local oscillator frequency
fref: phase comparison frequency
M:
main divider frequency division ratio
S:
swallow counter frequency division ratio
The variable frequency division ranges of M and S are as follows, and are set as binary.
S < M
≤
1023
0
≤
S
≤
31
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