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參數(shù)資料
| 型號(hào)： | CX77315 |
| 英文描述： | CX77315 Product Summary|PA Modules for GSM/GPRS Handsets |
| 中文描述： | CX77315產(chǎn)品概要|功率放大器模塊的GSM / GPRS手機(jī) |
| 文件頁(yè)數(shù)： | 13/14頁(yè) |
| 文件大小： | 517K |
| 代理商： | CX77315 |
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PA Module for Dual-band EGSM900 DCS1800 / GPRS
Data Sheet CX77301
100956E
Skyworks Solutions, Inc. Proprietary Information
[781] 376-7000 FAX [781] 376-3100 SALES@SKYWORKSINC.COM
WWW.SKYWORKSINC.COM
13
SEPTEMBER 19, 2003
an 8
μ
s delay, the amplifier internal bias will quickly ramp to
match the ramp voltage applied to the VAPC input. Since the bias
must be wide band relative to the power control loop, the ramp
will exhibit a fast edge rate. If the APC input increases beyond 1
volt before the 8
μ
s switching delay is allowed to occur after the
bias is enabled, the PA will have significant RF output as the
internal bias approaches the applied bias. During this ramp, the
internal power control is running "open loop" and the edge rates
are defined by the frequency response of the PA bias rather than
that of the power control loop. This open loop condition will result
in switching transients that are directly correlated to the PA bias
bandwidth.
Application of an initial APC voltage, which enables the bias at
least 8
μ
s before the VAPC voltage is ramped, will ensure that the
internal bias of the PAM will directly follow the applied VAPC. As a
result, the power control loop will define all edge transitions
rather than the PA internal bandwidth defining the transition.
Figure 10
and
Figure 11
show the relationship of the internal bias
relative to the applied APC in two cases. One case has ramping
starting from ground; the other case has ramping starting with an
initial enable pedestal of 700 mV. It is evident that the pedestal
level is critical to ensure a predictable and well behaved power
control loop.
To enable the CMOS driver in the PAM prior to ramp-up, a PAC
output pedestal level to the APC input of the PAM (pin 14) should
be set to about 700 mV. This pedestal level should have a
duration of at least 8
μ
s directly prior to the start of ramp up.
Figure 12
shows typical signals and timings measured in a GSM
transmitter power control loop. This particular example is at GSM
Power Level 5, Channel 62. The oscilloscope traces are
TxVCO_enable, PAC_enable, DAC Ramp, and VAPC (pin 14).
NOTE:
at the APC input of the PAM, then the PAC is enabled, and finally
the DAC ramp begins.
When the TxVCO is enabled, the pedestal becomes set
The device specifications for enable threshold level and switching
delay are shown in
Table 3
.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
5
10
15
20
25
30
35
Time (sec)
V
APC
In (V)
Internal Bias (V)
100956_011
Figure 10. PAM Internal Bias Performance – No Pedestal Applied
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
5
10
15
20
25
30
35
Time (sec)
B
V
APC
In (V)
Internal Bias (V)
100956_012
Figure 11. PAM Internal Bias Performance – Pedestal Applied
PAC_enable
V
APC
DAC Ramp
V
APC
Pedestal
TxVCO_enable
100956_013
Ch1
4
3
2
1
Ch3
A
M
Ch2
Ch4
200 mV
1.00 V
BW
500 mV
Ch2
10.0 μs
1.00 V
500 mV
T
Figure 12. GSM Transmitter – Typical Ramp-up Signals
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