參數(shù)資料
型號： CS61884-IRZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 27/72頁
文件大小： 0K
描述： IC LN INTERF T1/E1/J1 160-LFBGA
標準包裝： 126
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 8
電源電壓： 3.14 V ~ 3.47 V
功率（瓦特）： 1.73W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-LFBGA
供應商設備封裝： 160-TFGBA（13x13）
包裝： 散裝
包括： AMI 編碼器和解碼器，B8ZS 編碼器和解碼器，HDB3 編碼器和解碼器，LOS 檢測
產品目錄頁面： 759 (CN2011-ZH PDF)
其它名稱： 598-1717
CS61884
DS485F3
33
As illustrated in Figure 13, the ACB consists of a
R/W bit, address field, and two reserved bits. The
R/W bit specifies if the current register access is a
read (R/W = 1) or a write (R/W = 0) operation. The
address field specifies the register address from
0x00 to 0x1f.
13.3 Parallel Port Operation
Parallel port host mode operation is selected when
the MODE pin is high. In this mode, the CS61884
register set is accessed using an 8-bit, multiplexed
bidirectional address/data bus D[7:0]. Timing over
the parallel port is independent of the transmit and
receive system timing.
The device is compatible with both Intel and Mo-
torola bus formats. The Intel bus format is selected
when the MOT/INTL pin is high and the Motorola
bus format is selected when the MOT/INTL pin is
low. In either mode, the interface can have the ad-
dress and data multiplexed over the same 8-bit bus
or on separate busses. This operation is controlled
with the MUX pin; MUX = 1 means that the paral-
lel port has its address and data multiplexed over
the same bus; MUX = 0 defines a non-multiplexed
bus. The timing for the different modes are shown
Non-multiplexed Intel and Motorola modes are
Figure 33. The CS pin initiates the cycle, followed
by the DS, RD or WR pin. Data is latched into or
out of the part using the rising edge of the DS, WR
or RD pin. Raising CS ends the cycle.
Multiplexed Intel and Motorola modes are shown
read or write is initiated by writing an address byte
to D[7:0]. The device latches the address on the
falling edge of ALE(AS). During a read cycle, the
register data is output during the later portion of the
RD or DS pulses. The read cycle is terminated and
the bus returns to a high impedance state as RD
transitions high in Intel timing or DS transitions
high in Motorola timing. During a write cycle, val-
id write data must be present and held stable during
the WR or DS pulses.
In Intel mode, the RDY output pin is normally in a
high impedance state; it pulses low once to ac-
knowledge that the chip has been selected, and high
again to acknowledge that data has been written or
read. In Motorola mode, the ACK pin performs a
similar function; it drives high to indicate that the
address has been received by the part, and goes low
again to indicate that data has been written or read.
CS
SDI
SCLK
SDO
CLKE=0
0
R/W
00
0
1D0
D1
D2
D5
D3
D6
D4
D7
D0
D1
D2
D5
D3
D6
D4
D7
Address/Command Byte
Data Input/Output
Figure 13. Serial Read/Write Format (SPOL = 0)
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