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| 型號： | CS61881 |
| 英文描述： | Octal E1 Analog Front EndLine Interface Units |
| 中文描述： | 八路素E1模擬前端底線接口單元 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 461K |
| 代理商： | CS61881 |
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CS61881
12
DS451PP3
2.6.2 Test-Logic-Reset
The test-logic-reset state is used to disable the test
logic when the part is in normal mode of operation.
This state is entered by asynchronously asserting
TRSTB or forcing TMS High for 5 TCK periods.
2.6.3 Run-Test-Idle
The run-test-idle state is used to run tests.
2.6.4 Select-DR-Scan
This is a temporary controller state.
2.6.5 Capture-DR
In this state, the Boundary Scan Register captures
input pin data if the current instruction is EXTEST
or SAMPLE/PRELOAD.
2.6.6 Shift-DR
In this controller state, the active test data register
connected between TDI and TDO, as determined
by the current instruction, shifts data out on TDO
on each rising edge of TCK.
2.6.7 Exit1-DR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
2.6.8 Pause-DR
The pause state allows the test controller to tempo-
rarily halt the shifting of data through the current
test data register.
2.6.9 Exit2-DR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
2.6.10 Update-DR
The Boundary Scan Register is provided with a
latched parallel output to prevent changes while
data is shifted in response to the EXTEST and
SAMPLE/PRELOAD instructions. When the TAP
controller is in this state and the Boundary Scan
Register is selected, data is latched into the parallel
output of this register from the shift-register path
on the falling edge of TCK. The data held at the
latched parallel output changes only in this state.
2.6.11 Select-IR-Scan
This is a temporary controller state. The test data
register selected by the current instruction retains
its previous state.
2.6.12 Capture-IR
In this controller state, the instruction register is
loaded with a fixed value of "01" on the rising edge
of J-TCK. This supports fault-isolation of the
board-level serial test data path.
2.6.13 Shift-IR
In this state, the shift register contained in the in-
struction register is connected between TDI and
TDO and shifts data one stage towards its serial
output on each rising edge of TCK.
2.6.14 Exit1-IR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
2.6.15 Pause-IR
The pause state allows the test controller to tempo-
rarily halt the shifting of data through the instruc-
tion register.
2.6.16 Exit2-IR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
2.6.17 Update-IR
The instruction shifted into the instruction register
is latched into the parallel output from the shift-reg-
ister path on the falling edge of J-TCK. When the
new instruction has been latched, it becomes the
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| CS61884-IB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC Octal T1/E1/J1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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