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參數(shù)資料
| 型號： | CS5550-ISZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 15/15頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 2CH LOW-COST 24-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)差分，雙極 |
IDT / ICS HSTL FREQUENCY SYNTHESIZER
9
ICS8421002I REV B MARCH 02, 2009
ICS8421002I
FEMTOCLOCKS CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8421002I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8421002I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 122mA = 422.7mW
Power (outputs)
MAX
= 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 32.8mW = 65.6mW
Total Power
_MAX
(3.465V, with all outputs switching) = 422.7mW + 65.6mW = 488.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.488W * 66.6°C/W = 117.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθθθθ
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6. THERMAL RESISTANCE
θθθθθ
JA
FOR
20-PIN TSSOP, FORCED CONVECTION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5-56 | 制造商:SUPERWORLD 制造商全稱:Superworld Electronics 功能描述:POWER TRANSFORMER |
| CS5560 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:【2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ツヒ ADC |
| CS5560_08 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ΔΣ ADC |
| CS5560_09 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ΔΣ ADC |
| CS5560-ISZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit 50 kSps ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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