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參數(shù)資料
| 型號： | CS5513 |
| 元件分類： | 串行ADC |
| 英文描述： | CS5510/11/12/13 Product Data Sheet|DC Measurement|A/D Converters |
| 中文描述： | CS5510/11/12/13產(chǎn)品數(shù)據(jù)|直流測量| A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 20/26頁 |
| 文件大?。?/td> | 499K |
| 代理商： | CS5513 |
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CS5510/11/12/13
20
DS337F1
2.5.5
Multiplexed Applications
The settling performance of the CS5510/11/12/13
in multiplexed applications is determined by the
Sinc
4
filter. To settle a step input requires 4 full
conversion cycles after the analog input has
switched. In this case, the throughput is reduced by
a factor of four as the first three conversions after
the step is applied will not be fully settled.
If the application does not require the maximum
throughput possible from the ADC, the multiplexer
can be switched at any time. In this case, the system
must wait for at least five conversion cycles for a
fully-settled result from the ADC.
If maximum throughput is required in a multi-
plexed application, the multiplexer must be
switched at the correct time during the data collec-
tion process. For maximum throughput with the
CS5510/12, switching of a multiplexer should oc-
cur 595 SCLK cycles after SDO falls. For maxi-
mum throughput with the CS5511/13, switching of
a multiplexer should occur on the rising edge of
SDO during a conversion in which the data word is
not read. The conversion data that is immediately
available when SDO falls again is valid, and repre-
sents the analog input from the previous multiplex-
er setting. The next three conversions from the part
will be unsettled values, and the fourth conversion
will represent a fully-settled result from the new
multiplexer setting. The multiplexer should be
switched again at the appropriate time during the
third conversion cycle to ensure the maximum pos-
sible throughput.
2.6
The CS5510/11/12/13 exhibit excellent linearity
with low offset and gain drift, without the need for
calibration. If precision voltage measurements are
required by the system, however, software-based
offset and gain calibration can be performed by the
system.
Digital Off-Chip System Calibration
To perform a software offset calibration, the “zero-
point” of the system should be established by ap-
plying an input to the system equal to zero. Then,
the user can obtain a conversion and store it in
memory as the system’s zero point (ZP). This num-
ber can then be used as the zero point for any sub-
sequent conversion words. In the 20-bit devices
(CS5512 and CS5513), multiple conversions can
be averaged to arrive at a more accurate offset val-
ue. In the 16-bit devices (CS5510 and CS5511), av-
eraging may not be meaningful, because the noise
will be below the size of one LSB when using nom-
inal voltages for VREF (2.5 V).
A software gain calibration can be performed by
bringing the system to a known calibration Voltage
value (Vcal) and acquiring a conversion (note that
Vcal should be low enough to compensate for the
possible gain error of the ADC). Multiple conver-
sions can be averaged at this point to improve the
accuracy of the calibration. The code obtained from
this conversion is the real value (Cr) of the calibra-
tion Voltage input, and will differ from the ideal
value. The ideal value for this conversion (Ci) will
be equivalent to: 0x7FFF*Vcal/(0.80*Vref) for the
CS5510/11, and 0x7FFFF*Vcal/(0.80*Vref) for
the CS5512/13. The gain error (GE) is equal to: (Cr
- ZP)/Ci. To correct for both offset and gain error in
subsequent conversions, subtract the offset error,
and then divide by the gain error.
2.7
The CS5510/11/12/13 accommodates two power
consumption modes: normal and sleep. The normal
mode is the default mode and is entered after power
is established to the ADC. In normal mode, the
ADCs typically consumes 2.5 mW. Sleep is en-
tered when the user leaves SCLK high for at least
200
μ
s. The ADCs are guaranteed to be in sleep af-
ter SCLK is high (logic 1) for 2 ms. The sleep mode
reduces the consumed power to less than 10
μ
W
when CS is high (logic 1). If CS is low (logic 0) at
this time, the SDO drive logic will still be active,
Power Consumption, Sleep and Reset
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相關(guān)代理商/技術(shù)參數(shù) |
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| CS5513-BS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Delta Sigma ADC Int. OSC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5513-BSR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 20-Bit 8-Pin Delta Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5513-BSZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Delta Sigma ADC Int. OSC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5513-BSZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 20-Bit 8-Pin Delta Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5516 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16BIT/20-BIT BRIDGE TRANSDUCER A/D CONVERTER |
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