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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | CS5512-BSZ |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 22/26闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 20BIT EXTERNAL OSC 8-SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 100 |
| 浣嶆暩(sh霉)锛� | 20 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 326 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 2.5mW |
| 闆诲闆绘簮锛� | 闆� ± |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-SOIC锛�0.209"锛�5.30mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-SOIC |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 1 鍊嬪樊鍒�锛岄洐妤� |
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CS5510/11/12/13
DS337F4
5
ANALOG CHARACTERISTICS (Continued)
Notes: 8. VREF is referenced to V- and must be less than or equal to V+.
9. Due to current through the CS pin, IV+ and IV- may not always be the same value.
10. All outputs unloaded. All inputs CMOS levels (> (V+ - 0.6 V) or < (V- + 0.6 V)).
11. CS must be inactive (logic high) during sleep to meet this power specification.
DIGITAL CHARACTERISTICS
Notes: 12. All measurements performed under static conditions.
13. VL1 is 0.5 (V+ - V-) + 0.6 V + V-.
14. The CS signal provides the sink current path for the SDO pin when CS is low. The external drive logic
to CS, therefore, must be able to handle the logic-low current drive levels for all devices attached to
SDO. The voltage specified for SDO is relative to CSLow. See Section 2.3.1, 鈥淒igital Logic Levels鈥� and
Figure 11 for more details.
Parameter
Min
Typ
Max
Unit
Voltage Reference Input
Range
{(VREF) - (V-)}
(Note 8) 0.250
2.5
(V+) - (V-)
V
Input Capacitance
-
7
-
pF
CVF current
-
6
-
nA
Power Supplies
Supply Voltages
{(V+) - (V-)}
4.75
5
5.25
V
DC Power Supply Currents
(Note 9)
IV+
CS5510
CS5511
CS5512
CS5513
IV-
CS5510
CS5511
CS5512
CS5513
-
275
290
360
385
275
290
360
385
360
380
470
500
360
380
470
500
A
Power Consumption
(Note 10)
CS5510
CS5511
CS5512
CS5513
Sleep
(Note 11)
-
1.4
1.5
1.8
1.9
10
1.9
2.0
2.5
2.7
-
mW
W
Power Supply Rejection
dc Positive Supply
dc Negative Supply
-
85
-
dB
Parameter
Symbol
Min
Typ
Max
Unit
High-Level Input Voltage:
CS and SCLK
VIH
V+ - 0.45
-
V
Low-Level Input Voltage:
(Note 13) CS
SCLK
CSLow
VIL
-
VL1
V
Input Current:
(Note 14) CS
ICS
-
-1.0
mA
High-Level Output Voltage:
SDO, Isource = 5.0mA
VOH
(V+) - 0.6
-
V
Low-Level Output Voltage:
VOL
--
(CSLow) + 0.6
V
Input Leakage Current
SCLK
Iin
-
卤0.015
卤10
A
3-State Leakage Current
SCLK
IOZ
--
卤10
A
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