參數(shù)資料
型號(hào)： CS5376A-IQZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 31/49頁(yè)
文件大?。?/td> 0K
描述： IC FILTER DGTL MULTI-CH 64-TQFP
標(biāo)準(zhǔn)包裝： 160
濾波器類(lèi)型： 數(shù)字
濾波器數(shù)： 4
濾波器階數(shù)： 2nd
電源電壓： 3 V ~ 5 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 管件
配用： 598-1778-ND - EVALUATION BOARD FOR CS5376
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
37
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Field Name
Bits
Access
Reset
Description
Interface Protect
Disable
INTF_PROT_DIS
7
rd/wr/s/c
0b
Controls circuitry built into the FUSB2805 for protecting the
ULPI interface when the link three-states STP and D[7:0].
Any pull-ups or pull-downs employed by this feature can be
disabled. This bit is not intended to affect the operation of the
holding state. When this bit is enabled, the FUSB2805
automatically detects when the link stops driving STP.
0b: Enables the interface-protect circuit (default). A weak
pull-up resistor is attached to STP and, if STP is unexpectedly
HIGH, the FUSB2805 attaches weak pull-down resistors on
D[7:0] to protect the data inputs.
1b: Disables the interface-protect circuit. Detaches the weak
pull-down resistors on D[7:0] and weak pull-up on STP.
Refer to 3.12 of the ULPI Rev. 1.1, October 2004 specification
for details.
OTG Control Register
– OTG_CTRL (0Ah-0Ch Read, 0Ah Write, 0Bh Set, 0Ch Clear)
These registers control the UTMI+ OTG function settings of the FUSB2805.
Table 19. OTG Control Register
Field Name
Bits
Access Reset
Description
IDPullup
0
rd/wr/s/c
0b
Connects a pull-up to ID line and enables sampling the signal level;
0b: Disables sampling of ID pin
1b: Enables sampling of ID pin
DpPulldown
1
rd/wr/s/c
1b
Enables the 15
kΩ pull-down resistor on D+
0b: Pull-down resistor not connected to D+
1b: Pull-down resistor connected to D+
DmPulldown
2
rd/wr/s/c
1b
Enables the 15
kΩ pull-down resistor on D-
0b: Pull-down resistor not connected to D-
1b: Pull-down resistor connected to D-
DischrgVBUS
3
rd/wr/s/c
0b
Discharges VBUS through a resistor. A minimum of 656 Ω is defined in
the OTG specification. If the link sets this bit to 1b, it waits for an
RXCMD indicating SessEnd has transitioned from 0b to 1b, then resets
this bit to 0b to stop the discharge event.
0b: Do not discharge VBUS
1b: Discharge VBUS
ChrgVBUS
4
rd/wr/s/c
0b
Charges VBUS through a resistor. Used for VBUS pulsing SRP. A
minimum output impedance of 281
Ω with a voltage source of 3.0 V as
defined in the OTG specification can be used. The link must first check
that VBUS has been discharged (see DischrgVBUSbit) and that both D+
and D- have signaled an SE0 for a minimum of 2ms.
0b: Do not charge VBUS
1b: Charge VBUS
Reserved
5
rd/wr/s/c
0b
Reserved
DrvVBUS External
6
rd/wr/s/c
0b
Selects the external 5 V VBUS supply via PSW pin.
0b: Drive PSW LOW
1b: Drive PSW HIGH
UseExternalVBUS
Indicator
7
rd/wr/s/c
0b
Tells the FUSB2805 to use an external VBUS over-current indicator.
This bit is optional.
0b: Use the internal OTG comparator (VA_VBUS_VLD) or internal VBUS
valid indicator (default).
1b: Use external VBUS valid indicator signal on FAULT
Refer to 3.8.7.3 of the ULPI Rev. 1.1, October 2004 specification for
details.
Note:
23. Resistor termination implementations conform to USB2.0 resistor ECN.
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