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參數(shù)資料
| 型號： | CS5368-DQZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8CH 114DB 216KHZ 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 216k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.12W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個(gè)差分，單極 |
| 配用： | 598-1157-ND - BOARD EVAL FOR CS5368 192KHZ ADC |
DS624F4
15
CS5368
SERIAL AUDIO INTERFACE - IS/LJ TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.
Notes:
1.
Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System
2.
CLKMODE functionality described in Section 4.6.3
3.
In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, chip performance
is guaranteed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page
Figure 3. IS/LJ Timing
Parameter
Symbol
Min
Typ
Max
Unit
Sample Rates
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
-
2
54
108
-
54
108
216
kHz
Master Mode
SCLK Frequency
SCLK Period
1/(64*216 kHz)
SCLK Duty Cycle (Note 1)
(CLKMODE = 0)(Note 2)
(CLKMODE = 1)(Note 2)
-
tPERIOD
tHIGH
64*Fs
72.3
40
28
-
50
33
64*Fs
-
60
38
Hz
ns
%
LRCK setup
before SCLK rising
LRCK hold
after SCLK rising
tSETUP1
tHOLD1
20
--
ns
SDOUT setup
before SCLK rising
SDOUT hold
after SCLK rising (VLS = 1.8 V)
after SCLK rising (VLS = 3.3 V)
after SCLK rising (VLS = 5 V)
tSETUP2
tHOLD2
10
20
10
5
--
ns
Slave Mode
SCLK Frequency (Note 3)
SCLK Period
1/(64*216 kHz)
SCLK Duty Cycle
-
tPERIOD
tHIGH
-
72.3
28
64*Fs
-
65
Hz
ns
%
LRCK setup
before SCLK rising
LRCK hold
after SCLK rising
tSETUP1
tHOLD1
20
--
ns
SDOUT setup
before SCLK rising (VLS = 1.8 V)
before SCLK rising (VLS = 3.3 V)
before SCLK rising (VLS = 5 V)
SDOUT hold
after SCLK rising (VLS = 1.8 V)
after SCLK rising (VLS = 3.3 V)
after SCLK rising (VLS = 5 V)
tSETUP2
tHOLD2
4
10
20
10
5
--
ns
LRCK
SDOUT
SCLK
data
channel
data
t
HOLD2
t
SET UP2
t
HOLD1
t
SET UP1
t
PERIOD
t
HIGH
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5368-DQZR | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC IC 114dB 192kHz 8ch ADC w/TDM Intrfc RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
| CS5371 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, High-performance ΔΣ Modulators |
| CS5371_05 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, High-performance ΔΣ Modulators |
| CS5371A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, High-performance Modulators |
| CS5371A_09 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, High-performance ΔΣ Modulators |
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