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| 型號： | CS5361GD16 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 116K |
| 代理商： | CS5361GD16 |
CS5361
http://onsemi.com
7
PACKAGE PIN DESCRIPTION
Package Pin #
SO–16
Pin Symbol
Function
1
ENABLE/UVLO
Shutdown input. Connect to V
IN
through a resistor divider to program minimum operating
voltage. Pull below 2.5 V to shut down the IC.
2
OSC
Oscillator pin. Place resistor to GND to set the switching frequency. Enters bias mode when
pulled above 2.75 V and the ENABLE/UVLO Input is low (PFET turned ON).
3
V
REF(IN)
Reference input of the voltage error amplifier. Connect to the built–in or external reference.
4
LGND
Logic Ground. IC Substrate Connection.
5
I
COMP
Current feedback compensation network.
6
V
REF
4.2 V Reference output voltage. Capable of sourcing 3.0 mA.
7
I
AVG
Average current control loop input. Voltage at this pin sets average output current.
8
V
COMP
Voltage feedback compensation network.
9
V
FB
Voltage feedback pin. Connect a resistor divider between output and this pin to set output
voltage.
10
I
PEAK
Peak current control loop input. This input is used to set peak value of the inductor ripple
current. This pin can override average current loop setting. It can be used for fast current
control.
11
IS–
Negative input of the current sense amplifier.
12
IS+
Positive input of the current sense amplifier.
13
PGND
Power Ground.
14
GATE(L)
Low–Side FET Driver. This pin is capable of delivering peak currents of 1.0 A.
15
V
CC
Input power supply pin or V
CC
bias.
16
GATE(H)
High–Side FET Driver. This pin is capable of delivering peak currents of 1.0 A.
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