IDT / ICS 3.3V LVPECL CLOCK GENERATOR
參數(shù)資料
型號: CS5351-BZZ
廠商: Cirrus Logic Inc
文件頁數(shù): 15/16頁
文件大小: 0K
描述: IC ADC AUD 108DB 204KHZ 24-TSSOP
標(biāo)準(zhǔn)包裝: 62
位數(shù): 24
采樣率(每秒): 204k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 243mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
輸入數(shù)目和類型: 2 個單端,單極
配用: 598-1781-ND - EVALUATION BOARD FOR CS5351
其它名稱: 598-1084-5
IDT / ICS 3.3V LVPECL CLOCK GENERATOR
8
ICS843001AG REV B March 2, 2009
ICS843001
FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
FIGURE 2. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The ICS843001 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF
parallel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted
for different board layouts.
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843001 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC and VCCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
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