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參數(shù)資料
| 型號： | CS5233-3GDF8 |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS |
| 中文描述： | 三端固定電壓調(diào)節(jié)器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 95K |
| 代理商： | CS5233-3GDF8 |
CS5233–3
http://onsemi.com
8
needed extra current until the external power supply can
respond. One of the consequences of providing this current
is an instantaneous voltage drop at V
IN
due to capacitor
ESR. The magnitude of the voltage change is again the
product of the current change and the capacitor ESR.
It is very important to consider the maximum current step
that can exist in the system. If the change in current is large
enough, it is possible that the instantaneous voltage drop on
V
IN
will exceed the V
IN
threshold hysteresis, and the IC will
enter a mode of operation resembling an oscillation. As the
part turns on, the output current I
OUT
will increase, reaching
current limit during initial charging. Increasing I
OUT
results
in a drop at V
IN
such that the shutdown threshold is reached.
The part will turn off, and the load current will decrease. As
I
OUT
decreases, V
IN
will rise and the part will turn on,
starting the cycle all over again. This oscillatory operation
is most likely at initial start–up when the output capacitance
is not charged, and in cases where the ramp–up of the V
IN
supply is slow. It may also occur during the power transition
when the linear regulator turns on and the PFET turns off. A
20
μ
s delay exists between turn–on of the regulator and the
AuxDrv pin pulling the gate of the PFET high. This delay
prevents “chatter” during the power transitions.
If required, using a few capacitors in parallel to increase
the bulk charge storage and reduce the ESR should give
better performance than using a single input capacitor.
Short, straight connections between the power supply and
V
IN
lead along with careful layout of the PC board ground
plane will reduce parasitic inductance effects. Wide V
IN
and
V
OUT
traces will reduce resistive voltage drops.
Choosing the PFET Switch
The choice of the external PFET switch is based on two
main considerations. First, the PFET should have a very low
turn–on threshold. Choosing a switch transistor with
V
GS(ON)
≈
1.0 V will ensure the PFET will be fully enhanced
with only 3.3 V of gate drive voltage. Second, the switch
transistor should be chosen to have a low R
DS(ON)
to
minimize the voltage drop due to current flow in the switch.
The formula for calculating the maximum allowable
on–resistance is
RDS(ON)MAX
VAUX(MIN)
1.5
VOUT(MIN)
IOUT(MAX)
V
AUX(MIN)
is the minimum value of the auxiliary supply
voltage, V
OUT(MIN)
is the minimum allowable output
voltage, I
OUT(MAX)
is the maximum output current and 1.5
is a “fudge factor” to account for increases in R
DS(ON)
due
to temperature.
Output Voltage Sensing
It is not possible to remotely sense the output voltage of
the C5233–3 since the feedback path to the error amplifier
is not externally available. It is important to minimize
voltage drops due to metal resistance of high current PC
board traces. Such voltage drops can occur in both the
supply traces and the return traces.
The following board layout practices will help to
minimize output voltage errors:
Always place the linear regulator as close to both load
and output capacitors as possible.
Always use the widest possible traces to connect the
linear regulator to the capacitor network and to the
load.
Connect the load to ground through the widest possible
traces.
Connect the IC ground to the load ground trace at the
point where it connects to the load.
Current Limit
The CS5233–3 has internal current limit protection.
Output current is limited to a typical value of 3.0 A for the
D
2
PAK using V
IN
and 800 mA using V
SB
, even under output
short circuit conditions. If the load current drain exceeds the
current limit value, the output voltage will be pulled down
and will result in an out of regulation condition.
Thermal Shutdown
The CS5233–3 has internal temperature monitoring
circuitry. The output is disabled if junction temperature of
the IC reaches 180
°
C. Thermal hysteresis is typically 25
°
C
and allows the IC to recover from a thermal fault without the
need for an external reset signal. The monitoring circuitry is
located near the composite PNP–NPN output transistor,
since this transistor is responsible for most of the on–chip
power dissipation. The combination of current limit and
thermal shutdown will protect the IC from nearly any fault
condition.
Reverse Current Protection
During normal system operation, the auxiliary drive
circuitry will maintain voltage on the V
OUT
pin. IC
reliability and system efficiency are improved by limiting
the amount of reverse current that flows from V
OUT
to
ground and from V
OUT
to V
IN
. Current flows from V
OUT
to
ground through the feedback resistor divider that sets up the
output voltage, typically 400
μ
A. Current flow from V
OUT
to V
IN
will be limited to leakage current after the IC shuts
down. On–chip RC time constants are such that the output
transistor should be turned off well before V
IN
drops below
the V
OUT
voltage.
Calculating Power Dissipation and
Heatsink Requirements
Most linear regulators operate under conditions that result
in high on–chip power dissipation. This results in high
junction temperatures. Since the IC has a thermal shutdown
feature, ensuring the regulator will operate correctly under
normal conditions is an important design consideration.
Some heatsinking will usually be required.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS5233-3GDFR8 | THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS |
| CS5233-3GDP5 | THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS |
| CS5233-3GDPR5 | THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS |
| CS5317-TD | Analog-to-Digital Converter， 16-Bit |
| CS5317-BD | Analog-to-Digital Converter， 16-Bit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5233-3GDFR8 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:500 mA and 1.5 A, 3.3 V Dual Input Linear Regulator with Auxiliary Control |
| CS5233-3GDP5 | 制造商:ON Semiconductor 功能描述:500 mA and 1.5 A, 3.3 V Dual Input Linear Regulator with Auxiliary Control |
| CS5233-3GDPR5 | 功能描述:IC REG LDO 3.3V 1.5A D2PAK-5 RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性 系列:- 標準包裝:3,000 系列:- 穩(wěn)壓器拓撲結(jié)構(gòu):正，固定式和可調(diào)式 輸出電壓:3.3V，1.25 V ~ 5.7 V 輸入電壓:4.5 V ~ 7 V 電壓 - 壓降（標準）:1.1V @ 1A 穩(wěn)壓器數(shù)量:2 電流 - 輸出:1A 電流 - 限制（最?。?1A 工作溫度:0°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:TO-252-5，DPak（4 引線 + 接片），TO-252AD 供應(yīng)商設(shè)備封裝:PPAK 包裝:管件 其它名稱:497-3576-5 |
| CS5234-000 | 制造商:TE Connectivity 功能描述:EPD-RWC-21838 - Cable Rools/Shrink Tubing |
| CS5236-000 | 制造商:TE Connectivity 功能描述:EPD-RWC-21836 - Cable Rools/Shrink Tubing |
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