參數(shù)資料
型號(hào)： CS5165GDW16
廠商： ZF Electronics Corporation
英文描述： Fast, Precise 5-Bit Synchronous Buck Controller for the Next Generation Low Voltage Pentium II Processors
中文描述： 快速，精確的5位同步降壓控制器，用于下一代低電壓奔騰II處理器
文件頁數(shù)： 2/19頁
文件大小： 278K
代理商： CS5165GDW16
Absolute Maximum Ratings
Pin Symbol
V
CC
Pin Name
IC Power Input
V
MAX
V
MIN
I
SOURCE
I
SINK
2
PACKAGE PIN #
PIN SYMBOL
FUNCTION
Package Pin Description
C
16V
-0.3V
N/A
1.5A Peak
200mA DC
10μA
SS
Soft Start Capacitor
6V
-0.3V
200μA
COMP
Compensation Capacitor
6V
-0.3V
10mA
1mA
V
FB
Voltage Feedback Input
6V
-0.3V
10μA
10μA
C
OFF
Off-Time Capacitor
6V
-0.3V
1mA
50mA
V
ID0-4
Voltage ID DAC Inputs
6V
-0.3V
1mA
10μA
GATE(H)
High-Side FET Driver
16V
-0.3V
1.5A Peak;
200mA DC
1.5A Peak;
200mA DC
GATE(L)
Low-Side FET Driver
16V
-0.3V
1.5A Peak;
200mA DC
1.5A Peak;
200mA DC
ENABLE
Enable Input
6V
-0.3V
100μA
1mA
PWRGD
Power-Good Output
6V
-0.3V
10μA
30mA
PGnd
Power Ground
0V
0V
1.5A Peak
200mA DC
N/A
LGnd
Logic Ground
0V
0V
100mA
N/A
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 150°C
Lead Temperature Soldering:
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec max. above 183°C, 230°C Peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65°C to 150°C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
1,2,3,4,6
V
ID0
-V
ID4
Voltage ID DAC inputs. These pins are internally pulled up to 5V if left open.
V
ID4
selects the DAC range. When V
ID4
is high (logic one), the Error Amp ref-
erence range is 2.14V to 3.54V with 100mV increments. When V
ID4
is low (logic
zero), the Error amp reference voltage is 1.34V to 2.09V with 50mV increments.
Soft Start Pin. A capacitor from this pin to LGnd sets the Soft Start and fault
timing.
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets both the nor-
mal and extended off time.
Output Enable Input. This pin is internally pulled up to 1.8V. A logic Low
( < 0.8V) on this pin disables operation and places the CS5165 into a low cur-
rent sleep mode.
Input Power Supply Pin.
High Side Switch FET driver pin.
High Current ground for the GATE(H) and GATE(L) pins.
Low Side Synchronous FET driver pin.
Power Good Output. Open collector output drives low when V
FB
is out of
regulation. Active when ENABLE input is low
Reference ground. All control circuits are referenced to this pin.
Error Amp output. PWM Comparator reference input. A capacitor to LGnd
provides Error Amp compensation.
Error Amp, PWM Comparator, and Low V
FB
Comparator feedback input.
5
SS
7
C
OFF
8
ENABLE
9
10
11
12
13
V
CC
GATE(H)
PGnd
GATE(L)
PWRGD
14
15
LGnd
COMP
16
V
FB
相關(guān)PDF資料
PDF描述
CS5165GDWR16 Fast, Precise 5-Bit Synchronous Buck Controller for the Next Generation Low Voltage Pentium II Processors
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