2. PIN DESCRIPTIONS Pin Name # Pin Descriprion VDP 6 8 13 14 Digital Logic Power (I" />
參數(shù)資料
型號: CS4461-CZZ
廠商: Cirrus Logic Inc
文件頁數(shù): 8/11頁
文件大?。?/td> 0K
描述: IC ADC PSR FEEDBACK 24-TSSOP
標(biāo)準(zhǔn)包裝: 62
采樣率(每秒): 7.5M
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 235mW
電壓電源: 模擬和數(shù)字
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)差分,單極
產(chǎn)品目錄頁面: 758 (CN2011-ZH PDF)
其它名稱: 598-1069-5
6
DS650F1
CS4461
2. PIN DESCRIPTIONS
Pin Name
#
Pin Descriprion
VDP
6
8
13
14
Digital Logic Power (Input) – Digital core and input/output power supply. Nominally +3.3 V or +5.0 V.
Supply decoupling should placed as close as possible to pin 6.
VA
19
Analog Power (Input) - Analog power supply. Nominally +5.0 V.
GND
2
7
10
12
18
20
21
Ground (Input) - Ground reference for both analog and digital.
PSR_RESET
1
Reset (Input) - When PSR_RESET is low, the CS4461 enters a low power mode and all internal states
are reset. On initial power up, PSR_RESET must be held low until the power supply is stable, and all
input clocks are stable in frequency and phase.
VQ
22
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
REFGND
23
Reference Ground (Input) - Ground reference for the internal sampling circuits.
FILT+
24
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuit.
AIN+
AIN-
16
17
Differential PSR Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-
tor via the AIN+/- pins.
PSR_MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and output data.
PSR_SYNC
3
Synchronization Data Output (Output) - Used to synchronize the serial data in the PWM modulator.
PSR_DATA
4
PSR Serial Data Output (Output) - Power supply modulated and formatted serial data.
PSR_EN
11
PSR Enable (Input) - A high to low transition on this pin will enable the PSR feedback circuit.
OVERFLOW
15
Overflow (Output, open drain) - Indicates a modulator overflow condition.
TEST
9
Test (Output) - This pin may toggle during normal operation and should be pulled low through a 47 k
resistor to GND in order to minimize noise.
PSR_RESET
FILT+
GND
REFGND
PSR_SYNC
VQ
PSR_DATA
GND
PSR_MCLK
GND
VDP
VA
GND
VDP
AIN-
TEST
AIN+
GND
OVERFLOW
PSR_EN
VDP
GND
VDP
1
2
3
4
5
6
7
817
18
19
20
21
22
23
24
9
10
11
12
13
14
15
16
Top-Down View
24-pin TSSOP Package
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