參數(shù)資料
型號(hào): CS4461-CZZ
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 10/11頁(yè)
文件大小: 0K
描述: IC ADC PSR FEEDBACK 24-TSSOP
標(biāo)準(zhǔn)包裝: 62
采樣率(每秒): 7.5M
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 235mW
電壓電源: 模擬和數(shù)字
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)差分,單極
產(chǎn)品目錄頁(yè)面: 758 (CN2011-ZH PDF)
其它名稱: 598-1069-5
8
DS650F1
CS4461
4. APPLICATIONS
4.1
Digital Connections
PSR_MCLK provides the system clock for the CS4461. PSR_SYNC and PSR_DATA provide the output of
the modulator to the class-D modulator with feedback capabilities. Series damping resistors should be used
on PSR_MCLK, PSR_SYNC, and PSR_DATA to minimize noise. These should be placed as close as pos-
sible to their signal source. The pin labeled TEST should also be pulled low to GND through a 47 k
resistor
to minimize noise coupling into the ADC modulator.
4.2
Analog Connections
The analog modulator samples the input at PSR_MCLK/4 (6.144 MHz with PSR_MCLK=24.576 MHz).
Figure 2 shows the suggested analog input filter. This filter topology will correctly buffer the power supply’s
AC and DC components for PSR processing by the class-D modulator. The use of capacitors which have a
large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade sig-
nal linearity. C0G dielectrics should be used wherever possible. R1 and R2 should be used to scale VP
(class-D amplifier high voltage power supply) to less than the CS4461 maximum AIN+/AIN- input voltage
(3.9 V).
The following equation can be used to scale R1 and R2:
2 * (VP * (1 + %VP_Ripple)) * (R2 / (R1 + R2)) < 3.9 V
Example (VP = 40 V, %VP_Ripple = 4%):
2 * (40 * (1 + 0.04)) * (1.96 k
/ (40.2 k + 1.96 k) = 3.87 V
CS4461
AIN+
AIN-
2200 pF
C0G
-
+
90.9
120 pF
2 k
2 k
+5.0 V
649
90.9
+
-
+5.0 V
120 pF
649
VP
R1
R2
Figure 2. CS4461 Recommended Analog Input Buffer
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