參數(shù)資料
型號(hào): CS43L22-CNZ
廠商: Cirrus Logic Inc
文件頁數(shù): 33/66頁
文件大?。?/td> 0K
描述: IC DAC W/HDPN & SPKR AMPS 40QFN
標(biāo)準(zhǔn)包裝: 50
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
包裝: 托盤
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): 96k
產(chǎn)品目錄頁面: 756 (CN2011-ZH PDF)
配用: 598-1529-ND - BOARD EVAL FOR CS43L22
其它名稱: 598-1650
DS792F2
39
CS43L22
Confidential Draft
3/4/10
7.4.2
Speed Mode
Configures the speed mode of the DAC in Slave Mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in Master Mode.
Notes:
1.
Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 40.
2.
Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
page 39) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 39). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
3.
These bits are ignored when the AUTO bit (“Auto-Detect” on page 38) is enabled.
7.4.3
32kHz Sample Rate Group
Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
7.4.4
27 MHz Video Clock
Specifies whether or not the external MCLK frequency is 27 MHz
7.4.5
Internal MCLK/LRCK Ratio
Configures the internal MCLK/LRCK ratio.
SPEED[1:0]
Slave Mode
Master Mode
Serial Port Speed
MCLK/LRCK Ratio
SCLK/LRCK Ratio
00
Double-Speed Mode (DSM - 50 kHz -100 kHz Fs)
512
64
01
Single-Speed Mode (SSM - 4 kHz -50 kHz Fs)
256
64
10
Half-Speed Mode (HSM - 12.5kHz -25 kHz Fs)
128
64
11
Quarter-Speed Mode (QSM - 4 kHz -12.5 kHz Fs)
128
64
Application:
32kGROUP
8 kHz, 16 kHz or 32 kHz sample rate?
0
No
1Yes
Application:
VIDEOCLK
27 MHz MCLK?
0
No
1Yes
Application:
RATIO[1:0]
Internal MCLK Cycles per LRCK
SCLK/LRCK Ratio in Master Mode
00
128
64
01
125
62
10
132
66
11
136
68
Application:
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