參數(shù)資料
型號： CS4364-CQZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 21/50頁
文件大?。?/td> 0K
描述： IC DAC 103DB 24BIT 6CH 48-LQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 8
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 520mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
輸出數(shù)目和類型： 8 電壓，單極
采樣率（每秒）： 216k
產(chǎn)品目錄頁面： 757 (CN2011-ZH PDF)
配用： CDB4364-ND - EVALUATION BOARD FOR CS4364
其它名稱： 598-1059
28
DS619F1
CS4364
Figure 21. Recommended Mute Circuitry
4.12
Recommended Power-Up Sequence
4.12.1
Hardware Mode
1.
Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the
registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.
If RST can not be held low long enough the SDINx pins should remain static low until all other clocks
are stable, and if possible the RST should be toggled low again once the system is stable.
2.
Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the
Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024
LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.12.2
Software Mode
1.
Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default
settings, FILT+ will remain low, and VQ will be connected to VA/2.
2.
Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in
Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode).
3.
In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the
format and mode control bits to the desired settings.
If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will
enter Hardware Mode and begin to operate with the M0-M4 as the mode settings. CPEN bit may be
written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit
can not be set in time then the SDINx pins should remain static low (this way no audio data can be
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參數(shù)描述
CS4364-CQZR 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24b 6Ch DAC w/DSD Supt/Lw-Ltnc DF RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
CS4364-DQZ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:103 dB, 192 kHz 6-Channel D/A Converter
CS4364-DQZR 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:103 dB, 192 kHz 6-Channel D/A Converter
CS4365 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 6-Channel D/A Converter
CS4365_07 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 6-Channel D/A Converter
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