參數(shù)資料
型號： CS4360-KZZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 20/37頁
文件大?。?/td> 0K
描述： IC DAC STER 6CH 102DB 28TSSOP
標準包裝： 50
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 6
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 265mW
工作溫度： -10°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 28-TSSOP
包裝： 托盤
輸出數(shù)目和類型： 6 電壓，單極
采樣率（每秒）： 192k
產(chǎn)品目錄頁面： 757 (CN2011-ZH PDF)
其它名稱： 598-1642
CS4360
DS517F2
27
4.9.2b
IC Read
To read from the device, follow the procedure below while adhering to the control port Switching Specifi-
cations. During this operation it is first necessary to write to the device, specifying the appropriate register
through the MAP.
1) After writing to the MAP (see section 4.9.1), initiate a repeated START condition to the IC bus fol-
lowed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting
of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit.
2) Signal the end of the address byte by not issuing an acknowledge. The device will then transmit the
contents of the register pointed to by the MAP. The MAP will contain the address of the last register
written to the MAP.
3) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con-
tinue providing a clock but do not issue an ACK on the bytes clocked out of the device. After all the
desired registers are read, initiate a STOP condition to the bus.
4) If the INCR bit is set to 0 and further IC reads from other registers are desired, it is necessary to repeat
the procedure detailed from step 1. If no further reads from other registers are desired, initiate a STOP
condition to the bus.
4.9.3
SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see Figure 21 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the control port. When the device detects a high-to-low transition on the
AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
SD A
SC L
001000
A D 0
W
Sta rt
AC K
MA P
1-8
AC K
DA TA
1-8
AC K
Stop
Figure 19. IC Write
SD A
SC L
00 10 00
A D 0
W
Sta rt
AC K
MA P
1- 8
AC K
00 10 00
A D 0
R
R e p e a te d ST AR T
or
A b o rte d W R IT E
AC K
Da ta 1 -8
(poi nted to by M A P )
D a ta 1 -8
(p oi nted to by M A P )
AC K
Sto p
Figure 20. IC Read
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