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參數(shù)資料
| 型號： | CS4299-JQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 35/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AC 97 W/SRC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | SoundFusion™ |
| 類型： | 音頻編解碼器 '97 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 18 b，20 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 是 |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 85 / 87 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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CS4299
40
7. SONY/PHILIPS DIGITAL
INTERFACE (S/PDIF)
The S/PDIF digital output is used to interface the
CS4299 to consumer audio equipment external to
the PC. This output provides an interface for stor-
ing digital audio data or playing digital audio data
to digital speakers. Figure 20 illustrates the circuits
necessary for implementing the IEC-958 optical or
consumer interface. For further information on
S/PDIF operation see application note AN22: Over-
view of Digital Audio Interface Data Structures [3].
For further information on S/PDIF recommended
transformers see application note AN134: AES and
S/PDIF Recommended Transformers [4].
8. GROUNDING AND LAYOUT
Figure 21 on page 41 shows the conceptual layout
for the CS4299. The decoupling capacitors should
be located physically as close to the pins as possi-
ble. Also note the connection of the REFFLT de-
coupling capacitors to the ground return trace
connected directly to the ground return pin, AVss1.
It is strongly recommended that separate analog
and digital ground planes be used. Separate ground
planes keep digital noise and return currents from
modulating the CS4299 ground potential and de-
grading performance. The digital ground pins
should be connected to the digital ground plane and
kept separate from the analog ground connections
of the CS4299 and any other external analog cir-
cuitry. All analog components and traces should be
located over the analog ground plane and all digital
components and traces should be located over the
digital ground plane.
The common connection point between the two
ground planes (required to maintain a common
ground voltage potential) should be located under
the CS4299. The AC-link digital interface connec-
tion traces should be routed such that the digital
ground plane lies underneath these signals (on the
internal ground layer). This applies along the entire
length of these traces from the AC ’97 controller to
the CS4299.
Refer to the Application Note AN18: Layout and
Design Rules for Data Converters and Other
Mixed Signal Devices [2] for more information on
layout and design rules.
1
2
3
4
5
6
0.1
F
R
2
R
1
J1
DGND
DVdd
R
1
R
2
SPDO/SDO2
S/PDIF_OUT
TOTX-173
SPDO/SDO2
+5V_PCI
DGND
8.2 k
DGND
3.3V
247.5
107.6
5V
375
93.75
T
1
Figure 20. S/PDIF Output
40
DS319PP6
CS4299
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