
C
ONFIDENTIAL
DS588PP1 -
rev
0.4 April 11, 2002
Copyright
2002 Cirrus Logic Inc.
Pinout Information
P
RELIMINARY
D
RAFT
www.cirrus.com
15
Host
Interface
Signals (cont.)
DMARQ
DMACK*
PDIAG*
DASP*
SDCLK
CKE
DQMU
DQML
WE*
CS0*
CS1*
CAS*
RAS*
BA11
BA10
BA9
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
BD15
BD14
BD13
BD12
BD11
BD10
BD9/
PLL_CLK_BP_SL
BD8/
CS_POLARITY
BD7/
MOT-I*
BD6/
M-NM*
BD5/
DEC_CLK_BP_SL
BD4/
DTSL
BD3/
XTSL
BD2/
UCSL2
BD1/
UCSL1
BD0/
UCSL0
80
85
90
98
10
11
12
13
15
17
18
19
20
42
43
44
45
46
47
48
50
52
53
54
55
21
22
23
24
27
29
O -TS
I
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
DMA Request
DMA Acknowledge*
Passed Diagnostics*
Slave Present
SDRAM CLK
Clock Enable
Upper Data Mask Enable
Lower Data Mask Enable
Write Enable
Chip Select 0
Chip Select 1
Column Address Strobe Low
Row Address Strobe
Buffer
Interface
Signals
Buffer Address [11:0]
Buffer Data Bus
30
I/O
Buffer Data Bus Bit 9 / PLL Clock Bypass
31
32
33
I/O
I/O
I/O
Buffer Data Bus Bit 8 / uComputer Clock Select
Buffer Data Bus Bit 7 / Motorola-Intel
Buffer Data Bus Bit 6 / Multiplexed - Nonmultiplexed
34
I/O
Buffer Data Bus Bit 5 / Decoder Clock
35
36
38
40
41
I/O
I/O
Buffer Data Bus Bit 4 / Drive Test Select
Buffer Data Bus Bit3 / XTAL Select
I/O
Buffer Data Bus Bit 2-0 / uComputer Clock Select
Table 3: CL-CS3712 Pin Map (Continued)
Type
Name
Pin(s)
I/O
Function