Register Map
DS588PP1 -
rev
0.4 April 11, 2002
Copyright
2002 Cirrus Logic Inc.
C
ONFIDENTIAL
P
RELIMINARY
D
RAFT
www.cirrus.com
10
8CH
8DH
8EH
90H
91H
92H
93H
94H
95H
98H
99H
9AH
9BH
9CH
9DH
RAW Header/SubHeader Flag (HDFLG)
Header Read-Out Control (RDCTRL)
Data Channel Interface Configuration 3 (DCCFG3)
Disc Interrupt Status 1 (DIST1)
Disc Interrupt Enable 1 (DIEN1)
Disc Interrupt Status 2 (DIST2)
Disc Interrupt Enable 2 (DIEN2)
Disc Transfer Control 1 (DCTRL1)
Sector Per Track Count (SPTC)
BCA Control 1
BCA Status 1
BCA Control 2
BCA Control 3
BCA Control 4
BCA Channel Clock
Spindle Speed
Defect Address FIFO1/FIFO2(DMF)
C1/C2 Control (C12CNTL)
EFM Sync Control (EFMSYCTL)
EFM Plus Sync Control (EFMPSYCTL)
Subcode Read-Out (SBRD)
Subcode Control/Status (SBCTL)
EFM Plus Sync Status (EFMPSYNSTS)
Corrected ID Read-Out (CIDR)
SRAM Diagnostics Status 1 (SRAMST1)
SRAM Diagnostics Status 2 (SRAMST2)
SRAM Diagnostics Status 3 (SRAMST3)
SRAM Diagnostics Control 1 (SRAMDIACTL1)
SRAM Diagnostics Control 2 (SRAMDIACTL2)
SRAM uC Access Data (SRAMUPDATA)
SRAM uC Access Address (SRAMUPADDR)
Test1 (TEST)
Product and Revision Number (PRVN)
Miscellaneous Control (MISC)
Power Control
Clock Selection
RF ADC Diagnostic Control 1
RF ADC Diagnostic Control 2
Analog Diagnostic
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
9EH-9FH
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BDH
BEH
BFH
C0H
C1H
C2H
C3H
C4H
Table 1: CL-CS3712 Registers
Address (Hex)
Register Name
R/W