參數(shù)資料
型號: CS235GDWR18
廠商: ZF Electronics Corporation
英文描述: System Photoelectric Smoke Detector
中文描述: 系統(tǒng)光電感煙探測器
文件頁數(shù): 1/6頁
文件大小: 147K
代理商: CS235GDWR18
Features
GATE
POWER
UP
GATE BIAS
SET
MAIN
LED
DRIVER
OSCILLATOR
CURRENT
LIMITER
OUTPUT
LATCH
COUNTER
D3
CLOCK
POWER UP BIAS
COMP
SYNC
DETECTOR
A2
A1
DET
REF
DET
OUT
NC
A2
OUT
A2
IN
L.L.
GND
A1 IN
(+)
A1 IN
(-)
INT
BIAS
OSC
PGM
TIMER
CAP
PGM
RES
PULSE
WIDTH
LED H.L.
Gnd
V
R
I
PGM
V
/
OUT
I
Synchronous Detection
for High Noise Immunity
Pulsed Operation for Low
Average Current Drain
System Gain Externally
Set
System Sensitivity
Externally Adjustable
System Operation
Monitored by Means of
External Red LED
I
I
I
I
Package Options
C
System Photoelectric Smoke Detector
Description
CS235
The CS235 System Smoke Detector
is a photo electric type with a
pulsed infrared LED as the light
source and a silicon photodiode as
the light detector. The CS235 IC,
along with passive external compo-
nents, controls the system timing
and signal processing.
Low average current is attained by
pulsing the system once every 10
seconds for 20 milliseconds. Bias is
applied to the signal processing cir-
cuitry for this time interval. During
the second half of the pulse, the last
10 milliseconds, the IR LED is
pulsed and the unit samples for an
alarm level smoke condition. After
the first alarm level signal the sam-
ple rate increases to a two second
interval. After three consecutive
alarm level samples the logic drives
the output latch signalling the sys-
tem panel.
The signal processing circuit blocks
are amplifiers A1 and A2, syn-
chronous detector, voltage com-
parator and the decode counter.
The voltage gain of A2 and the
comparator reference voltage are
set by external resistors.
Additional on-chip features include
an I
CC
current limiter. The current
limiter eliminates power-on false
alarming.
The oscillator controls the IR LED
excitation frequency and provides
drive to the synchronous detector.
The synchronous detection method
has very high noise rejection perfor-
mance.
The internal latch is capable of sink-
ing 100 milliamps maximum and
will clamp the V
CC
pin to 5 volts
when tripped. The latch current is
determined by an external resistor
typically located in the master
panel and is reset by temporary
removal of detector power.
Block Diagram
1
Timer
Pulse Width
2
3
4
5
6
7
8
I
CC
Program
V
CC
/Output
Hi Level GND
A1 Input (-)
A1 Input (+)
LO Level GND
A2 Input
16
15
14
13
12
11
10
Timer Cap
Timer Period
Program
V REG
LED Output
Oscillator
Program
Internal Bias
NC
Detector Output
9
A2 Output
Detector
Reference
17
18
18 Lead PDIP & SOIC Wide
1
A
Company
¨
Rev. 7/6/98
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
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