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參數資料
| 型號： | CR16MCT5VJE7Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數： | 116/157頁 |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16MCT5VJE7Y |
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The critical path derives from receiving a remote frame which
triggers the transmission of one or more data frames. There
are a minimum of four bit times in-between two consecutive
frames. These bit times start at the validation point of re-
ceived frame (reception of 6th EOF bit) and end at the earli-
est possible transmission start of the next frame, which is
after the third intermission bit at 100% burst bus load.
These four bit times have to be set in perspective with the
timing requirements of the CR16CAN.
The minimum duration of the four CAN bit times is deter-
mined by the following Bit Time Logic settings:
PSC = PSCmin = 2
TSEG1 = TSEG1min = 2
TSEG2 = TSEG2min = 1
bit time = Synch + Time Segment 1 + Time Segment 2
= (1 + 2 + 1) tq = 4 tq
= (4 tq x PSC) clock cycles
= (4 tq x 2) clock cycles = 8 clock cycles
For these minimum BTL settings, four CAN bit times take 32
clock cycles.
The following is an example that assumes typical case:
— minimum BTL settings
— reception and copy of a remote frame
— update of one buffer from TX_RTR
— schedule of one buffer from transmit
As outlined in Table 39 the copy process, update and sched-
uling the next transmission gives a total of 17+3+2=22 clock
cycles. Therefore under these conditions there is no timing
restriction.
The following example assumes the worst case:
— minimum BTL settings
— reception and copy of a remote frame
— update of the 14 remaining buffers from TX_RTR
— schedule of one buffer for transmit
All these actions in total require 17 + 14 x 3 + 2 = 61 clock
cycles to be executed by CR16CAN. This leads to the limita-
tion of the Bit Time Logic of 61 / 4 = 15.25 clock cycles per
CAN bit as a minimum, resulting in the minimum clock fre-
quencies listed below (the frequency depends on the desired
baud rate and assumes the worst case scenario can occur in
the application).
Table 40 gives examples for the minimum clock frequency in
order to ensure proper functionality at various CAN bus
speeds.
Table 40
Min. Clock Frequency Requirements
20.10.4 Bit Time Logic Calculation Examples
The calculation of the CAN bus clocks using CKI = 16MHz is
shown in the following examples. The desired baud rate for
both examples is 1Mbit/s.
Example 1
PSC = PSC[5:0] + 2 = 0 + 2 = 2
TSEG1 = TSEG1[3:0] + 1 = 3 + 1 = 4
TSEG2 = TSEG2[2:0] + 1 = 2 + 1 = 3
SJW = TSEG2 = 3
— sample point positioned at 62.5% of bit time
— bit time = 125ns x (1 + 4 + 3 ± 3) = (1 ± 0.375)ms
— busclock = 16MHz / (2 x (1 + 4 + 3)) = 1Mbit/s (nominal)
Example 2
PSC = PSC[5:0] + 1 = 2 + 2 = 4
TSEG1 = TSEG1[3:0] + 1 = 1 + 1 = 2
TSEG2 = TSEG2[2:0] + 1 = 0 + 1 = 1
SJW = TSEG2 = 1
sample point positioned at 75% of bit time
bit time = 250ns x (1 + 2 + 1 ± 1) = (1 ± 0.25)ms
busclock = 16MHz / (2 x (1 + 4 + 3)) = 1Mbit/s (nominal)
20.10.5 Acceptance Filter Considerations
The CR16CAN provides two acceptance filter masks GMSK
and BMSK as described in Acceptance Filtering on page 95,
Global Mask Registers (GMSK — GMSKB and GMSKX) on
page 111 and Basic Mask Registers (BMSK — BMSKB and
BMSKX) on page 112. These masks allow filtering of up to 32
bits of the message object, which includes the standard iden-
tifier, the extended identifier as well as the frame control bits
RTR, SRR and IDE.
20.10.6 Remote Frames
Remote frames can be automatically processed by the
CR16CAN interface. However, to fully enable that feature,
the RTR/XRTR bits (for both standard and extended frames)
within the BMSK and/or GMSK register need to be set to
“don’t care”. This is because a remote frame with the RTR bit
being set to “1” should trigger the transmission of a data
frame with the RTR bit set to “0” and therefore the ID bits of
the received message need to pass through the acceptance
filter. The same applies to transmitting remote frames and
switching to receive the corresponding data frames.
Baud Rate
min. clock frequency
1Mbit/sec
15.25MHz
500kbit/sec
7.625MHz
250kbit/sec
3,81MHz
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| CR16HCS5VJE8 | Microcontroller |
| CR16HCS9VJE7Y | Microcontroller |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CR16MCT5VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MCT5VJE9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16MCT5VJEXY | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16MCT9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| CR16MCT9VJE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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