參數(shù)資料
型號： CR16MCT5VJE7Y
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 103/157頁
文件大?。?/td> 1256K
代理商： CR16MCT5VJE7Y
103
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CIPND register (read only) and can be cleared by resetting
the flags in the CICLR registers.
20.7.1
In order to reduce decoding time of the CIPND register, the
buffer interrupt request with the highest priority is placed as
interrupt status code into the IST[3:0] section of the CSTPND
register.
Each of the buffer interrupts as well as the error interrupt can
be individually enabled or disabled in the CAN Interrupt En-
able register (CIEN). As soon as an interrupt condition oc-
curs, every interrupt request is indicated by a flag in the CAN
Interrupt Pending register (CIPND). When the interrupt code
logic for the present highest priority interrupt request is en-
abled, this interrupt will be translated into the IST[3:0] bits of
the CAN Status Pending register (CSTPND). An interrupt re-
quest can be cleared by setting the corresponding bit in the
CAN Interrupt Clear register (CICLR) to ‘1’.
Figure 67 illustrates the CR16CAN interrupt management.
Highest Priority Interrupt Code
The highest priority interrupt source is translated into the bits
IRQ and IST[3:0] as shown in Table 24.
Table 24
Highest Priority Interrupt Code (ICEN=FFFF)
CAN interrupt
request
IRQ
IST3
IST2
IST1
IST0
no request
0
0
0
0
0
Error interrupt
1
0
0
0
0
Buffer 0
1
0
0
0
1
Buffer 1
1
0
0
1
0
Buffer 2
1
0
0
1
1
Buffer 3
1
0
1
0
0
Buffer 4
1
0
1
0
1
Buffer 5
1
0
1
1
0
Buffer 6
1
0
1
1
1
Buffer 7
1
1
0
0
0
Figure 67.
CR16CAN Interrupt Management
CIPND
IST0
IST1
IST2
IST3
ICODE
clear interrupt flags of every
message buffer individually
IRQ
CICLR
CIEN
CICEN
Buffer 8
1
1
0
0
1
Buffer 9
1
1
0
1
0
Buffer 10
1
1
0
1
1
Buffer 11
1
1
1
0
0
Buffer 12
1
1
1
0
1
Buffer 13
1
1
1
1
0
Buffer 14
1
1
1
1
1
Table 24
Highest Priority Interrupt Code (ICEN=FFFF)
CAN interrupt
request
IRQ
IST3
IST2
IST1
IST0
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